S. Tam

Clock generation and distribution for the third generation Itanium/spl reg/ processor

S. Tam, U. Desai, R. Limaye, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

Clock generation and distribution for the first IA-64 microprocessor

S. Tam, S. Rusu, S. Tam, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

Clock generation and distribution for the 130-nm Itanium/sup /spl reg// 2 processor with 6-MB on-die L3 cache

S. Tam, R.D. Limaye, U.N. Desai, 2004, IEEE Journal of Solid-State Circuits.

Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache

S. Tam, R. Limaye, S. Choy, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

Package clock distribution design optimization for high-speed and low-power VLSIs

S. Tam, Qing Zhu, 1997 .

A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor

S. Tam, S. Rusu, J. Chang, 2005, IEEE Journal of Solid-State Circuits.

A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache

S. Tam, S. Rusu, H. Muljono, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache

S. Tam, S. Rusu, H. Muljono, 2007, IEEE Journal of Solid-State Circuits.

A 65nm 95W Dual-Core Multi-Threaded Xeon® Processor with L3 Cache

S. Tam, S. Rusu, J. Chang, 2006, 2006 IEEE Asian Solid-State Circuits Conference.