Suraj Sindia

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Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests

Vishwani D. Agrawal, Suraj Sindia, V. Agrawal, 2015, J. Electron. Test..

Innovative practices session 2C: New technologies, new challenges - 2

Suraj Sindia, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Impact of process variations on computers used for image processing

Vishwani D. Agrawal, Foster F. Dai, Virendra Singh, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing

Vishwani D. Agrawal, Virendra Singh, Suraj Sindia, 2012, Journal of Electronic Testing.

Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients

Vishwani D. Agrawal, Virendra Singh, Suraj Sindia, 2010, 2010 23rd International Conference on VLSI Design.

Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients

Vishwani D. Agrawal, Virendra Singh, Suraj Sindia, 2011, 29th VLSI Test Symposium.

Test and Diagnosis of Analog Circuits Using Moment Generating Functions

Vishwani D. Agrawal, Virendra Singh, Suraj Sindia, 2011, 2011 Asian Test Symposium.

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

High Sensitivity Signatures for Test and Diagnosis of Analog, Mixed-Signal and Radio-Frequency Circuits

Suraj Sindia, S. Sindia, 2013 .

High sensitivity test signatures for unconventional analog circuit test paradigms

Vishwani D. Agrawal, Suraj Sindia, 2013, 2013 IEEE International Test Conference (ITC).

Towards spatial fault resilience in array processors

Vishwani D. Agrawal, Suraj Sindia, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

Collision prevention for virtual reality systems

Zhen Yao, Songnan Yang, Suraj Sindia, 2016 .

Specification test minimization for given defect level

Vishwani D. Agrawal, Suraj Sindia, 2014, 2014 15th Latin American Test Workshop - LATW.

A Test Time Theorem and its Applications

Vishwani D. Agrawal, Praveen Venkataramani, Suraj Sindia, 2013, 2013 14th Latin American Test Workshop - LATW.

Tailoring Tests for Functional Binning of Integrated Circuits

Vishwani D. Agrawal, Suraj Sindia, 2012, 2012 IEEE 21st Asian Test Symposium.

About the cover from the Publication Co-Chairs

Suraj Sindia, Annaji Row Garimella, 2014, VLSID 2014.

Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients

Vishwani D. Agrawal, Virendra Singh, Suraj Sindia, 2009, 2009 Asian Test Symposium.

A test time theorem and its applications

Vishwani D. Agrawal, Praveen Venkataramani, Suraj Sindia, 2013, 2013 14th Latin American Test Workshop - LATW.

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Vishwani D. Agrawal, Virendra Singh, Suraj Sindia, 2009 .

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

Neural Network Guided Spatial Fault Resilience in Array Processors

Vishwani D. Agrawal, Suraj Sindia, S. Sindia, 2013, Journal of Electronic Testing.

Finding best voltage and frequency to shorten power-constrained test time

Vishwani D. Agrawal, Praveen Venkataramani, Suraj Sindia, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Wireless Power Transfer (WPT) by Magnetic Induction

Zhen Yao, Suraj Sindia, Mark Briggs, 2018 .

Testing linear and non-linear analog circuits using moment generating functions

Vishwani D. Agrawal, Virendra Singh, Suraj Sindia, 2011, 2011 12th Latin American Test Workshop (LATW).

Distinguishing process variation induced faults from manufacturing defects in analog circuits using V-transform coefficients

Vishwani D. Agrawal, Virendra Singh, Suraj Sindia, 2011, 2011 IEEE 43rd Southeastern Symposium on System Theory.

Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients

Vishwani D. Agrawal, Virendra Singh, Suraj Sindia, 2012, J. Electron. Test..