Hiroyuki Yamauchi

发表

Tadashi Otsuki, Toshi T. Doi, Hiroyuki Yamauchi, 1982 .

High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM (Special Section on High Speed and High Density Multi Functional LSI Memories)

Hiroyuki Yamauchi, Toshiaki Tsuji, T. Suzuki, 1994 .

A RTN variation tolerant guard band design for a deeper nanometer scaled SRAM screening test: Based on EM Gaussians mixtures approximations model of long-tail distributions

Hiroyuki Yamauchi, Worawit Somha, 2013, 2013 14th Latin American Test Workshop - LATW.

A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies

Hiroyuki Yamauchi, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Discussion on RTN Variation Tolerant Guard Band Design Based on Approximation Models of Long-Tail Distributions for Nano-Scaled SRAM Screening Test

Hiroyuki Yamauchi, Worawit Somha, 2013 .

A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era

Hiroyuki Yamauchi, 2009 .

On the Hidden-surface Problem and Half-tone Computer Graphics Representations

Hiroyuki Yamauchi, Setsuo Osuga, 1974 .

A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme

Meng-Fan Chang, Hiroyuki Yamauchi, Chien-Fu Chen, 2017, IEEE Journal of Solid-State Circuits.

Convolution/deconvolution SRAM analyses for complex gamma mixtures RTN distributions

Hiroyuki Yamauchi, Worawit Somha, 2013, Proceedings of 2013 International Conference on IC Design & Technology (ICICDT).

A variation tolerant SRAM circuit design with elevated cell biasing scheme for nanometer CMOS era

Hiroyuki Yamauchi, 2010 .

Special section on VLSI design technology in the sub-100 nm era

Makoto Nagata, Akira Matsuzawa, Mototsugu Hamada, 2006 .

A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme

Hiroyuki Yamauchi, Hironori Akamatsu, Toshikazu Suzuki, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation

Hiroyuki Yamauchi, Worawit Somha, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

A 45nm dual-port SRAM with write and read capability enhancement at low voltage

Hiroyuki Yamauchi, Y. H. Chen, Hung-Jen Liao, 2007, 2007 IEEE International SOC Conference.

An Adaptively Segmented Forward Problem Based Non-Blind Deconvolution Technique for Analyzing SRAM Margin Variation Effects

Hiroyuki Yamauchi, Worawit Somha, 2014 .

Data transmission system with differential data transfer

Hiroyuki Yamauchi, Hironori Akamatsu, 1999 .

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics

Hiroyuki Yamauchi, Toru Iwata, Takefumi Yoshikawa, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A large σVTH/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme

Meng-Fan Chang, Hiroyuki Yamauchi, Yuan-Hua Chu, 2010, 2010 Symposium on VLSI Circuits.

Data transmission device between computer nodes

Hiroyuki Yamauchi, Hironori Akamatsu, Takashi Hirata, 1999 .

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory

Meng-Fan Chang, Hiroyuki Yamauchi, Che-Wei Wu, 2011, 2011 IEEE International Solid-State Circuits Conference.

An RTN Variation Tolerant SRAM Screening Test Design with Gaussian Mixtures Approximations of Long-Tail Distributions

Hiroyuki Yamauchi, Worawit Somha, 2014, J. Electron. Test..

A filter design for blind deconvolution to decouple unknown RDF/RTN factors from complexly coupled SRAM margin variations

Hiroyuki Yamauchi, Worawit Somha, 2016, 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS).

A Low Power Complete Charge-Recycling Bus Architecture for Ultra-High Data Rate Ulsi's

Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation

Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami, 2006, IEICE Trans. Electron..

A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

Akira Matsuzawa, Hiroyuki Yamauchi, Toru Iwata, 1996, ISLPED.

A sub-0.5 /spl mu/A/MB data-retention DRAM

Hiroyuki Yamauchi, Toru Iwata, Masanori Fukumoto, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions

Hiroyuki Yamauchi, Worawit Somha, Ma YuYu, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Feedback gain phase alignment effects on convergence characteristics in Lucy-Richardson deconvolution for inversely predicting complex-shaped RTN distributions

Hiroyuki Yamauchi, Worawit Somha, H. Yamauchi, 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).

A mutual rectification-interference avoidance technique with cascade filters for both downward-direction tailed-RDF deconvolution

Hiroyuki Yamauchi, Worawit Somha, 2016, 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI).

Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs

Hiroyuki Yamauchi, Worawit Somha, 2015, 2015 16th Latin-American Test Symposium (LATS).

Multi-layer logic — A predicate logic including data structure as knowledge representation language

Setsuo Ohsuga, Hiroyuki Yamauchi, S. Ohsuga, 1986, New Generation Computing.

Embedded SRAM Design in Nanometer-Scale Technologies

Hiroyuki Yamauchi, H. Yamauchi, 2009 .

A Nano-Scaled SRAM Guard Band Design with Gaussian Mixtures Model of Complex Long Tail RTN Distributions

Hiroyuki Yamauchi, Worawit Somha, 2013 .

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Meng-Fan Chang, Hiroyuki Yamauchi, Che-Wei Wu, 2013, IEEE Journal of Solid-State Circuits.

An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's(Special Issue on the 1994 VLSI Circuits Symposium)

Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita, 1995 .

A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

Meng-Fan Chang, Hiroyuki Yamauchi, Yuan-Hua Chu, 2011, IEEE Journal of Solid-State Circuits.

A Look up Table Based Adaptive Segmentation Gaussian Mixtures Model for Fitting Complex Long-Tail RTN Distributions

Hiroyuki Yamauchi, Worawit Somha, H. Yamauchi, 2013 .

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_{\rm TH}$ Read-Port, and Offset Cell VDD Biasing Techniques

Meng-Fan Chang, Shu-Meng Yang, Hiroyuki Yamauchi, 2013, IEEE Journal of Solid-State Circuits.

Blind deconvolution technique for extracting unknown two factors of RTN and truncated RDF from given target for overall SRAM margin variations

Hiroyuki Yamauchi, Worawit Somha, Ma Yuyu, 2013, 2013 International SoC Design Conference (ISOCC).

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

A. Ueno, Hiroyuki Yamauchi, Toshio Yamada, 1988 .

A 40nm fully functional SRAM with BL swing and WL pulse measurement scheme for eliminating a need for additional sensing tolerance margins

Meng-Fan Chang, Ping Wang, Hiroyuki Yamauchi, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI

Hiroyuki Yamauchi, Toshiaki Kawasaki, Ryuji Nishihara, 2007, IEICE Trans. Electron..

Keynote Speech 1 MTDT 2009 Variation Tolerant SRAM Circuit Design Trend in a Deeper Nanometer-Scale Technology

Hiroyuki Yamauchi, 2009 .

Application of Local Network Concept to Audio Equipment

Hiroyuki Yamauchi, Toshiaki Setogawa, Hiroyuki Fujikura, 1986 .

A Technique to Circumvent V-shaped Deconvolution Error for Time-dependent SRAM Margin Analyses

Hiroyuki Yamauchi, Worawit Somha, Ma Yuyu, 2013 .

Prospects for variation tolerant SRAM circuit designs

Hiroyuki Yamauchi, 2009, 2009 IEEE 8th International Conference on ASIC.

A differential data aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications

Meng-Fan Chang, Hiroyuki Yamauchi, Jui-Jen Wu, 2009, 2009 Symposium on VLSI Circuits.

A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses

Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami, 2007, IEICE Trans. Electron..

A 28mn 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell

Meng-Fan Chang, Hiroyuki Yamauchi, Cheng-Xin Xue, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier

Hiroyuki Yamauchi, Hironori Akamatsu, Toshikazu Suzuki, 2005, IEICE Trans. Electron..

A technique to solve issue of Richardson-Lucy deconvolution for analyzing RTN effects on SRAM margin variation

Hiroyuki Yamauchi, Worawit Somha, 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems.

Keynote Speech 1

Hiroyuki Yamauchi, 2009 .

A Ultra Low Power Charge-Recyding Bus Architecture for Super High Data-Rate ULSI′s

Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita, 1994 .

Development and operation of GIS exercise materials for undergraduate students

Takashi Oguchi, Hiroyuki Yamauchi, Toshikazu Seto, 2018, PeerJ Prepr..

Losse Coupling of KAUS with Existing RDBMSs

Setsuo Ohsuga, Hiroyuki Yamauchi, 1990, Data Knowl. Eng..

A parallel filter technique to stabilize error-rectification behavior in RDF deconvolution process for SRAM screening test

Hiroyuki Yamauchi, Worawit Somha, 2016, 2016 SAI Computing Conference (SAI).

A Low Power Bus Architecture with Local and Global Charge-Recycling Bus Techniques for Battery-Operated Ultra-High Data Rate ULSI's

Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita, 1995 .

A filter design to increase accuracy of Lucy-Richardson deconvolution for analyzing RTN mixtures effects on VLSI reliability margin

Hiroyuki Yamauchi, Worawit Somha, Yuan-Qiang Song, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells (Special Issue on Low-Power LSI Technologies)

Hiroyuki Yamauchi, Toru Iwata, 1996 .

Incorporating Fuzzy Set Theory and Matrix Logic in Multi-Layer Logic - A Preliminary Consideration

Setsuo Ohsuga, Hiroyuki Yamauchi, S. Ohsuga, 1999, RSFDGrC.

A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current

Hiroyuki Yamauchi, Toru Iwata, Akito Uno, 1995, IEEE J. Solid State Circuits.

A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms

Meng-Fan Chang, Hiroyuki Yamauchi, Shyh-Shyuan Sheu, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM

Meng-Fan Chang, Ping Wang, Hiroyuki Yamauchi, 2012, IEEE Journal of Solid-State Circuits.

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

Meng-Fan Chang, Shu-Meng Yang, Hiroyuki Yamauchi, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications

Meng-Fan Chang, Guo-Wei Huang, Hiroyuki Yamauchi, 2018, IEEE Electron Device Letters.

A Comparative Study on RTN Deconvolution of Richardson-Lucy and Proposed Partitioned Means for Analyzing SRAM Fail-Bit Prediction Accuracy

Hiroyuki Yamauchi, Worawit Somha, 2014 .

A Circuit Tee nology for a Self- AM with Less than 0.5 ~A/ etention Current

Hiroyuki Yamauchi, Tsutomu Fujita, Akito Uno, 1995 .

Processing of Syntax and Semantics of Natural Language by Predicate Logic of Predicate Logic

Hiroyuki Yamauchi, H. Yamauchi, 1980, COLING.

Comparative study on deconvolution function dependencies of RTN/RDF effect estimation errors in analyzing sub-nm-scaled SRAM margins

Hiroyuki Yamauchi, Worawit Somha, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device

Meng-Fan Chang, Hiroyuki Yamauchi, Shyh-Shyuan Sheu, 2012, 17th Asia and South Pacific Design Automation Conference.

A Method and Language for Constructing Multiagent Systems

Setsuo Ohsuga, Hiroyuki Yamauchi, S. Ohsuga, 2000, ISMIS.

A 0.5 V/100 MHz over-V/sub CC/ grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

Akira Matsuzawa, Hiroyuki Yamauchi, Toru Iwata, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture

Akira Matsuzawa, Hiroyuki Yamauchi, Toru Iwata, 1997, IEEE Trans. Very Large Scale Integr. Syst..

A Comparative Study for Estimation Errors of RTN Effects by Matlab Built-in Deconvolution Functions

Hiroyuki Yamauchi, Worawit Somha, 2014 .

A phase shifting multiple filter design methodology for Lucy-Richardson deconvolution of log-mixtures complex RTN tail distribution

Hiroyuki Yamauchi, Worawit Somha, 2015, 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI).

Prospects of variation tolerant SRAM circuit designs for nanometer CMOS era

Hiroyuki Yamauchi, H. Yamauchi, 2009 .

Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs

Hiroyuki Yamauchi, Worawit Somha, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

Studies on Low Power Technologies for Battery-Operated Semiconductor Random Access Memories

Hiroyuki Yamauchi, H. Yamauchi, 1997 .

An Error Reduction Technique in Richardson-Lucy Deconvolution Method

Hiroyuki Yamauchi, Worawit Somha, H. Yamauchi, 2018, Journal of Physics: Conference Series.

A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers

Hiroyuki Yamauchi, Michihiro Inoue, T. Yamada, 1990 .

A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques

Meng-Fan Chang, Shu-Meng Yang, Hiroyuki Yamauchi, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A 20ns battery-operated 16Mb CMOS DRAM

Hiroyuki Yamauchi, H. Yamauchi, 1993 .

Iterative and adaptively segmented forward problem based non-blind deconvolution technique for analyzing SRAM margin variation effects

Hiroyuki Yamauchi, Worawit Somha, Ma Yuyu, 2013, 2013 International SoC Design Conference (ISOCC).

A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

Meng-Fan Chang, Hiroyuki Yamauchi, Cheng-Xin Xue, 2019, IEEE Journal of Solid-State Circuits.

A review and prospect of area scaling trend for SRAM circuit design solution in deeper nano-meter era

Hiroyuki Yamauchi, 2009 .

Container of an RFID relay antenna includes and method for arranging a plurality of these containers

Kenji Suzuki, Hiroyuki Yamauchi, Toshio Watanabe, 2005 .

DIGITAL AUDIO DELAY UNIT

Hiroyuki Yamauchi, 1981 .

ISSCC97 / SESSION 17 I TD: LOW-POWER I LOW-VOLTAGE CIRCUITS / PAPER SA 17.3

Akira Matsuzawa, Hiroyuki Yamauchi, Toru Iwata, 1997 .

A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Meng-Fan Chang, Hiroyuki Yamauchi, Yung-Chi Chen, 2009, IEEE Journal of Solid-State Circuits.

Apparatus and method for compressing audio and / or video data

Hiroyuki Yamauchi, Kenji Mori, Toshiaki Setogawa, 1996 .

Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement

Meng-Fan Chang, Shu-Meng Yang, Hiroyuki Yamauchi, 2013, IEEE Journal of Solid-State Circuits.

17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme

Meng-Fan Chang, Hiroyuki Yamauchi, Chien-Fu Chen, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A Layer-Wise Ensemble Technique for Binary Neural Network

Hiroyuki Yamauchi, Jiazhen Xi, 2021, Int. J. Pattern Recognit. Artif. Intell..

A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency

Hiroyuki Yamauchi, Lai-Fu Chen, Meng-Fan Chang, 2013, 2013 Symposium on VLSI Circuits.

A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency

Hiroyuki Yamauchi, Lai-Fu Chen, Meng-Fan Chang, 2013, 2013 Symposium on VLSI Technology.