Karam S. Chatha

发表

Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique

Glenn Leary, Krishnan Srinivasan, Krishna Mehta, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures

Krishnan Srinivasan, Karam S. Chatha, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Scheduling of synchronous data flow models on scratchpad memory based embedded processors

Karam S. Chatha, Weijia Che, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

Karam S. Chatha, Christopher Ostler, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Session details: Performance enhancement-new techniques for FPGAs and partitioning

Karam S. Chatha, Reinaldo Bergamaschi, 2008, CODES+ISSS '08.

Throughput optimal task allocation under thermal constraints for multi-core processors

Sarma B. K. Vrudhula, Ravishankar Rao, Karam S. Chatha, 2009, 2009 46th ACM/IEEE Design Automation Conference.

MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs

Ranga Vemuri, Karam S. Chatha, R. Vemuri, 2001, Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571).

Performance optimal speed control of multi-core processors under thermal constraints

Sarma B. K. Vrudhula, Karam S. Chatha, Vinay Hanumaiah, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Approximation algorithm for the temperature-aware scheduling problem

Karam S. Chatha, Sushu Zhang, Sushu Zhang, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

A power and performance model for network-on-chip architectures

Karam S. Chatha, Nilanjan Banerjee, Praveen Vellanki, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

An iterative algorithm for partitioning and scheduling of area constrained HW-SW systems

Ranga Vemuri, Karam S. Chatha, 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

Near optimal battery-aware energy management

Karam S. Chatha, Goran Konjevod, Sushu Zhang, 2009, ISLPED.

SAGA: synthesis technique for guaranteed throughput NoC architectures

Krishnan Srinivasan, Karam S. Chatha, 2005, ASP-DAC.

Scheduling of synchronous data flow models on scratchpad memory based embedded processors

Karam S. Chatha, Weijia Che, 2010, ICCAD 2010.

Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures

Karam S. Chatha, Sushu Zhang, Sushu Zhang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Layout aware design of mesh based NoC architectures

Krishnan Srinivasan, Karam S. Chatha, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

System-level thermal aware design of applications with uncertain execution time

Karam S. Chatha, Sushu Zhang, 2008, ICCAD 2008.

A methodology for layout aware design and optimization of custom network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha, K. Srinivasan, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Hardware-software partitioning and pipelined scheduling of transformative applications

Ranga Vemuri, Karam S. Chatha, R. Vemuri, 2002, IEEE Trans. Very Large Scale Integr. Syst..

System level methodology for programming CMP based multi-threaded network processor architectures

Karam S. Chatha, Christopher Ostler, Vijaykumar Ramamurthi, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures

Karam S. Chatha, Christopher Ostler, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Performance evaluation tool for rapid prototyping of hardware-software codesigns

Ranga Vemuri, Karam S. Chatha, 1998, Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237).

System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC

Glenn Leary, Karam S. Chatha, Weijia Che, 2012, DAC Design Automation Conference 2012.

Scheduling of stream programs onto SPM enhanced processors with code overlay

Karam S. Chatha, Weijia Che, 2011, 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia.

Performance and resource optimization of NoC router architecture for master and slave IP cores

Glenn Leary, Krishna Mehta, Karam S. Chatha, 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Dynamic scheduling of stream programs on embedded multi-core processors

Karam S. Chatha, Weijia Che, Haeseung Lee, 2012, CODES+ISSS '12.

Hardware-Software Codesign for Dynamically Reconfigurable Architectures

Ranga Vemuri, Karam S. Chatha, 1999, FPL.

Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints

Krishnan Srinivasan, Karam S. Chatha, K. Srinivasan, 2007, Integr..

A technique for throughput and register optimization during resource constrained pipelined scheduling

Karam S. Chatha, Nagendran Rangan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

System-level thermal aware design of applications with uncertain execution time

Karam S. Chatha, Sushu Zhang, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures

K. Selçuk Candan, Karam S. Chatha, Lina Peng, 2004, Multimedia Information Systems.

Linear-programming-based techniques for synthesis of network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

ISIS: a genetic algorithm based technique for custom on-chip interconnection network synthesis

Krishnan Srinivasan, Karam S. Chatha, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

A tool for partitioning and pipelined scheduling of hardware-software systems

Ranga Vemuri, Karam S. Chatha, 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).

Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance

Glenn Leary, Karam S. Chatha, 2010, 2010 23rd International Conference on VLSI Design.

An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling

Ranga Vemuri, Karam S. Chatha, 2000, Des. Autom. Embed. Syst..

Modular Design of Media Retrieval Workflows Using ARIA

K. Selçuk Candan, Karam S. Chatha, Maria Luisa Sapino, 2006, CIVR.

Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Karam S. Chatha, Nilanjan Banerjee, Praveen Vellanki, 2005, Integr..

An embedded co-processor architecture for energy-efficient stream computing

Karam S. Chatha, Amrit Panda, 2014, 2014 IEEE 12th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia).

An automated technique for topology and route generation of application specific on-chip interconnection networks

Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

NOCS 2011: Message from the general and program chairs

Radu Marculescu, Ran Ginosar, Michael Kishinevsky, 2011 .

An Embedded Architecture for Energy-Efficient Stream Computing

Karam S. Chatha, Amrit Panda, 2014, IEEE Embedded Systems Letters.

Guest Editors' Introduction - Special Issue on Network-on-Chip

Ran Ginosar, Karam S. Chatha, 2014, IEEE Trans. Computers.

Circuits and systems for real-time security and copyright protection of multimedia

Nasir D. Memon, Saraju P. Mohanty, Karam S. Chatha, 2009, Comput. Electr. Eng..

Power reduction via macroblock prioritization for power aware H.264 video applications

Baoxin Li, Karam S. Chatha, Michael A. Baker, 2008, CODES+ISSS '08.

Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control

Sarma B. K. Vrudhula, Karam S. Chatha, Vinay Hanumaiah, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

System-level design techniques for throughput and power optimization of multiprocessor SoC architectures

Krishnan Srinivasan, Karam S. Chatha, Nagender Telkar, 2004, IEEE Computer Society Annual Symposium on VLSI.

Compilation of stream programs for multicore processors that incorporate scratchpad memories

Karam S. Chatha, Weijia Che, Amrit Panda, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

A lightweight run-time scheduler for multitasking multicore stream applications

Karam S. Chatha, Michael A. Baker, 2010, 2010 IEEE International Conference on Computer Design.

A performance model and code overlay generator for scratchpad enhanced embedded processors

Karam S. Chatha, Amrit Panda, Michael A. Baker, 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures

Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A holistic approach to Network-on-Chip synthesis

Glenn Leary, Karam S. Chatha, 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming

Karam S. Chatha, Weijia Che, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures

Krishnan Srinivasan, Karam S. Chatha, K. Srinivasan, 2004, 17th International Conference on VLSI Design. Proceedings..

ILP and heuristic techniques for system-level design on network processor architectures

Krishnan Srinivasan, Karam S. Chatha, Christopher Ostler, 2007, TODE.

Approximation Algorithm for Process Mapping on Network Processor Architectures

Karam S. Chatha, Goran Konjevod, Christopher Ostler, 2007, 2007 Asia and South Pacific Design Automation Conference.

Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules

Karam S. Chatha, Goran Konjevod, Sushu Zhang, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

System-Level Design of Network-on-Chip Architectures ∗

Krishnan Srinivasan, Karam S. Chatha, K. Srinivasan, 2007 .

Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms

Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod, 2007, 2007 Asia and South Pacific Design Automation Conference.

Thermal aware task sequencing on embedded processors

Karam S. Chatha, Sushu Zhang, Sushu Zhang, 2010, Design Automation Conference.

Smart driver for power reduction in next generation bistable electrophoretic display technology

Aviral Shrivastava, Karam S. Chatha, Michael A. Baker, 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Automated technique for design of NoC with minimal communication latency

Glenn Leary, Karam S. Chatha, 2009, CODES+ISSS '09.

Quality-of-service and error control techniques for network-on-chip architectures

Karam S. Chatha, Nilanjan Banerjee, Praveen Vellanki, 2004, GLSVLSI '04.

A technique for energy versus quality of service trade-off for MPEG-2 decoder

Krishnan Srinivasan, Karam S. Chatha, Vijay Ramamurthi, 2004, IEEE Computer Society Annual Symposium on VLSI.

Session details: Advanced NoC design techniques

Petru Eles, Karam S. Chatha, 2008, CODES+ISSS '08.

Media processing workflow design and execution with ARIA

K. Selçuk Candan, Karam S. Chatha, Hari Sundaram, 2005, MULTIMEDIA '05.

A technique for low energy mapping and routing in network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha, K. Srinivasan, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Optimization of media processing workflows with adaptive operator behaviors

K. Selçuk Candan, Karam S. Chatha, Lina Peng, 2007, Multimedia Tools and Applications.

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

Radu Marculescu, Karam S. Chatha, Ran Ginosar, 2011, NOCS 2011.

Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine

Karam S. Chatha, Weijia Che, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors

Sarma B. K. Vrudhula, Karam S. Chatha, Vinay Hanumaiah, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A scalable parallel H.264 decoder on the cell broadband engine architecture

Sarma B. K. Vrudhula, Karam S. Chatha, Michael A. Baker, 2009, CODES+ISSS '09.

ARIA: an adaptive and programmable media-flow architecture for interactive arts

K. Selçuk Candan, Karam S. Chatha, Hari Sundaram, 2004, MULTIMEDIA '04.

Unrolling and retiming of stream applications onto embedded multicore processors

Karam S. Chatha, Weijia Che, 2012, DAC Design Automation Conference 2012.

Linear programming based techniques for synthesis of network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod, 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Approximation algorithm for the temperature-aware scheduling problem

Karam S. Chatha, Sushu Zhang, Sushu Zhang, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns

Ranga Vemuri, Karam S. Chatha, R. Vemuri, 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

Approximation algorithm for the temperature-aware scheduling problem

Karam S. Chatha, Sushu Zhang, 2007, ICCAD 2007.

Hardware-software Codesign for Dynamically Reconngurable Architectures ?

Karam S. Chatha, 1999 .