U. Bhattacharya

Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optic transmission

Mark J. W. Rodwell, R. Pullela, U. Bhattacharya, 1996 .

A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications

M. Bohr, U. Bhattacharya, K. Zhang, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

G. Curello, W. Hafez, M. Kang, 2012, 2012 International Electron Devices Meeting.

An 18 Mb, 12.3 GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

U. Bhattacharya, N. Nintunze, Cangsang Zhao, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

Yong-Gee Ng, Yih Wang, Zhanping Chen, 2009, IEEE Journal of Solid-State Circuits.

A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm2 1T1C bit cell

Zhanping Chen, Sangwoo Pae, W. Hafez, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

N. Vallepalli, M. Bohr, U. Bhattacharya, 2005, IEEE Journal of Solid-State Circuits.

SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

N. Vallepalli, U. Bhattacharya, K. Zhang, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply

N. Vallepalli, M. Bohr, U. Bhattacharya, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Active probes for on-wafer millimeter-wave network analysis

Mark J. W. Rodwell, U. Bhattacharya, R. Yu, 1994, Proceedings of Conference on Precision Electromagnetic Measurements Digest.

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

N. Vallepalli, M. Bohr, U. Bhattacharya, 2005, IEEE Journal of Solid-State Circuits.

The impact of assist-circuit design for 22nm SRAM and beyond

Zheng Guo, Yong-Gee Ng, U. Bhattacharya, 2012, 2012 International Electron Devices Meeting.