W. Lee

A New Failure Mechanism of MLC NOR Flash Memory Caused by Aggravated Drain Disturb Due to Co-Salicidation Process

S. B. Jeon, Kinam Kim, W. Kwon, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

Impact of floating gate dry etching on erase characteristics in NOR flash memory

Kang-Deog Suh, Yonghan Roh, W.H. Lee, 2002, IEEE Electron Device Letters.

Data retention failure in NOR flash memory cells

K. Suh, Keonsoo Kim, W. Lee, 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

Influence of plasma edge damage on erase characteristics of NOR flash EEPROM using channel erase method

Kang-Deog Suh, Yonghan Roh, Woung-Moo Lee, 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

M. Belyansky, L. Black, J. Holt, 2006, 2009 Symposium on VLSI Technology.

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

G. Burbach, D. Greenlaw, S.F. Huang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

The effect of dimensional scaling on the erase characteristics of NOR flash memory

W. Lee, 2003, IEEE Electron Device Letters.

Dual stress liner enhancement in hybrid orientation technology

M. Ieong, T. Kanarsky, D. Chidambarrao, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..