N. Badereddine

Scan Cell Reordering for Peak Power Reduction during Test Cycles

P. Girard, C. Landrault, S. Pravossoudovitch, 2006 .

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

A. Bosio, P. Girard, S. Pravossoudovitch, 2012, Journal of Electronic Testing.

Test solution for data retention faults in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics

P. Girard, A. Virazel, C. Landrault, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, PATMOS.

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, VLSI-SoC.

A statistical simulation method for reliability analysis of SRAM core-cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, Design Automation Conference.