J. Machillot

Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

H. Mertens, R. Ritzenthaler, M. Kim, 2018, International Electron Devices Meeting.

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Scaled, Novel Effective Workfunction Metal Gate Stacks for Advanced Low-VT, Gate-All-Around Vertically Stacked Nanosheet FETs with Reduced Vertical Distance between Sheets

H. Mertens, R. Ritzenthaler, M. Kim, 2019, Extended Abstracts of the 2019 International Conference on Solid State Devices and Materials.

Low Resistance Cu Vias for 24nm Pitch and Beyond

M. H. van der Veen, N. Jourdan, O. Pedreira, 2022, International Interconnect Technology Conference.