P. Yeh

Viable deep-submicron FD/SOI CMOS design for low-voltage applications

J. Fossum, P. Yeh, 1994, Proceedings. IEEE International SOI Conference.

Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology

Jerry G. Fossum, Ping Chin Yeh, J. Fossum, 1995 .

3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

M. H. Lee, S. S. Sheu, H. Y. Lee, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Advantages and challenges of high performance CMOS on SOI

D. Wristers, Darin Chan, Mario M. Pelella, 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

Subthreshold MOSFET conduction model and optimal scaling for deep-submicron fully depleted SOI CMOS

J. Fossum, P. Yeh, 1993, Proceedings of 1993 IEEE International SOI Conference.