R. Graham

Constructing Zero-deficiency Parallel Prefix Circuits of Minimum Depth

Chung-Kuan Cheng, Haikun Zhu, R. Graham, 2005 .

A hierarchical three-way interconnect architecture for hexagonal processors

Feng Zhou, Ronald L. Graham, Chung-Kuan Cheng, 2003, SLIP '03.

Balancing the interconnect topology for arrays of processors between cost and power

Feng Zhou, Ronald L. Graham, Chung-Kuan Cheng, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Tree Structures and Algorithms for Physical Design

Ronald L. Graham, Chung-Kuan Cheng, Dongwon Park, 2018, ISPD.

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Physical synthesis of bus matrix for high bandwidth low power on-chip communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2010, ISPD '10.

Three-dimensional Floorplan Representations by Using Corner Links and Partial Order

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2018, ACM Trans. Design Autom. Electr. Syst..

Floorplan representations: Complexity and connections

Ronald L. Graham, Chung-Kuan Cheng, Bo Yao, 2003, TODE.

3-D floorplanning using labeled tree and dual sequences

Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, 2008, ISPD '08.

Revisiting floorplan representations

Ronald L. Graham, Chung-Kuan Cheng, Bo Yao, 2001, ISPD '01.

3D floorplan representations: Corner links and partial order

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Tree Structures and Algorithms for Physical Design

Chung-Kuan Cheng, Ilgweon Kang, Dongwon Park, 2018, ISPD.