Jianyu Chen

An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic

H. P. Hofstee, Z. Al-Ars, Jinho Lee, 2020, Journal of Signal Processing Systems.

A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model

H. Peter Hofstee, Zaid Al-Ars, Jinho Lee, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress

H. Peter Hofstee, Jan Hidders, Zaid Al-Ars, 2018, CODES+ISSS.

Work-in-Progress: A High-Bandwidth Snappy Decompressor in Reconfigurable Logic

Jan Hidders, Zaid Al-Ars, Jian Fang, 2018, 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Refine and Recycle: A Method to Increase Decompression Parallelism

H. Peter Hofstee, Zaid Al-Ars, Jinho Lee, 2019, 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

FPGA Acceleration of Zstd Compression Algorithm

Zaid Al-Ars, Jianyu Chen, Maurice Daverveldt, 2021, 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

A matrix-multiply unit for posits in reconfigurable logic leveraging (open)CAPI

H. Peter Hofstee, Zaid Al-Ars, Jianyu Chen, 2018 .