M. Ueda

A 14bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40MS/s

H. Matsui, M. Ueda, M. Daito, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

H. Matsui, M. Ueda, M. Daito, 2006, IEEE Journal of Solid-State Circuits.

FPGA implementation of a blind source separation system based on stochastic computing

M. Ueda, M. Hori, 2008, 2008 IEEE Conference on Soft Computing in Industrial Applications.

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

H. Matsui, M. Ueda, M. Daito, 2006, IEEE Journal of Solid-State Circuits.