Baris Taskin

发表

Skew analysis and design methodologies for improved performance of resonant clocking

Vinayak Honkote, Baris Taskin, 2009, 2009 International SoC Design Conference (ISOCC).

Skew-bounded low swing clock tree optimization

Baris Taskin, Can Sitik, 2013, GLSVLSI '13.

Clock Skew Scheduling of Level-Sensitive Circuits

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2009 .

Wireless NoCs Using Directional and Substrate Propagation Antennas

Baris Taskin, Kapil R. Dandekar, Vasil Pano, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Design-for-Debug: A Vital Aspect in Education

Baris Taskin, Prawat Nagvajara, 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis

Baris Taskin, Scott Lerner, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

PEEC based parasitic modeling for power analysis on custom rotary rings

Vinayak Honkote, Baris Taskin, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Delay Insertion and Clock Skew Scheduling

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2009 .

Charge recovery logic for thermal harvesting applications

Baris Taskin, Leo Filippini, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

TSV‐based antenna for on‐chip wireless communication

Baris Taskin, Kapil R. Dandekar, Vasil Pano, 2020 .

Delay Insertion Method in Clock Skew Scheduling

Baris Taskin, Ivan S. Kourtev, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Clock Skew Scheduling in Rotary Clocking Technology

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2009 .

Simulation based study of wireless RF interconnects for practical CMOs implementation

Baris Taskin, Ankit More, 2010, SLIP '10.

A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion

Baris Taskin, Leo Filippini, B. Taskin, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Energy aware routing of multi-level Network-on-Chip traffic

Baris Taskin, Vasil Pano, Isikcan Yilmaz, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

FinFET - Based Low Swing Rotary Traveling Wave Oscillators

Baris Taskin, Ragh Kuttappa, 2020, ISCAS.

Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array

Vinayak Honkote, Baris Taskin, 2010, 2010 23rd International Conference on VLSI Design.

A charge recovery logic system bus

Baris Taskin, Leo Filippini, 2017, 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Wireless Network-on-Chip analysis of propagation technique for on-chip communication

Baris Taskin, Kapil R. Dandekar, Vasil Pano, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

A microcontroller-based embedded system design course with PSoC3

Baris Taskin, Prawat Nagvajara, Can Sitik, 2013, 2013 IEEE International Conference on Microelectronic Systems Education (MSE).

Multi-voltage domain clock mesh design

Baris Taskin, Can Sitik, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Vertical Arbitration-Free 3-D NoCs

Baris Taskin, Vasil Pano, Ankit More, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping

Baris Taskin, Ankit More, Mark Hempstead, 2015, 2015 28th International Conference on VLSI Design.

Integrated Clock Mesh Synthesis With Incremental Register Placement

Baris Taskin, Jianchao Lu, Xiaomi Mao, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Novel Static D-Flip-Flop Topology for Low Swing Clocking

Baris Taskin, Emre Salman, Can Sitik, 2015, ACM Great Lakes Symposium on VLSI.

Steiner tree based rotary clock routing with bounded skew and capacitive load balancing

Vinayak Honkote, Baris Taskin, Xin Chen, 2011, 2011 Design, Automation & Test in Europe.

ZeROA: Zero Clock Skew Rotary Oscillatory Array

Vinayak Honkote, Baris Taskin, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Capacitive load balancing for mobius implementation of standing wave oscillator

Vinayak Honkote, Baris Taskin, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

Wireless on Networks-on-Chip

Baris Taskin, 2013, 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

3-D Parasitic Modeling for Rotary Interconnects

Vinayak Honkote, Baris Taskin, Ankit More, 2012, 2012 25th International Conference on VLSI Design.

Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking

Baris Taskin, Ivan S. Kourtev, John Wood, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Multi-corner multi-voltage domain clock mesh design

Baris Taskin, Can Sitik, 2013, GLSVLSI '13.

Range-based dynamic routing of hierarchical on chip network traffic

Baris Taskin, Julian Kemmerer, 2014, 2014 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Robust Low Power Clock Synchronization for Multi-Die Systems

Baris Taskin, Vasil Pano, Ioannis Savidis, 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Uncore RPD: Rapid design space exploration of the uncore via regression modeling

Baris Taskin, Mark Hempstead, Karthik Sangaiah, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation

Baris Taskin, Selçuk Köse, Longfei Wang, 2019, 2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Incremental register placement for low power CTS

Baris Taskin, Jianchao Lu, 2009, 2009 International SoC Design Conference (ISOCC).

Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking

Baris Taskin, Vasil Pano, Leo Filippini, 2020, ISCAS.

Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits

Baris Taskin, Ivan S. Kourtev, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits

Baris Taskin, Jianchao Lu, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Session details: Energy Efficient Systems

Baris Taskin, 2015, GLSVLSI 2015.

Clock buffer polarity assignment with skew tuning

Baris Taskin, Jianchao Lu, 2011, TODE.

A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs

Baris Taskin, Ankit More, 2012, SLIP '12.

Stability of Rotary Traveling Wave Oscillators under process variations and NBTI

Baris Taskin, Scott Lerner, Leo Filippini, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Design automation scheme for wirelength analysis of resonant clocking technologies

Vinayak Honkote, Baris Taskin, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016

Baris Taskin, Tsung-Yi Ho, 2017, Integr..

Clock mesh synthesis method using the Earth Mover's Distance under transformations

Baris Taskin, Ying Teng, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Reconfigurable threshold logic gates using optoelectronic capacitors

Baris Taskin, Bahram Nabet, Lunal Khuon, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Resonant frequency divider design methodology for dynamic frequency scaling

Baris Taskin, Ying Teng, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

Frequency-centric resonant rotary clock distribution network design

Baris Taskin, Ying Teng, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip

Baris Taskin, Ankit More, 2011, SLIP '11.

Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement

Baris Taskin, Vasil Pano, Isikcan Yilmaz, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

SnackNoC: Processing in the Communication Layer

Baris Taskin, Mark Hempstead, Ragh Kuttappa, 2020, 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Network-on-chip (noc) architectures for exa-scale chip-multi-processors (cmps)

Baris Taskin, Ankit More, 2013 .

Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation

Baris Taskin, Ankit More, Mark Hempstead, 2015, 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Post-CTS Delay Insertion

Baris Taskin, Jianchao Lu, Jianchao Lu, 2010, VLSI Design.

Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits

Baris Taskin, Ivan S. Kourtev, 2009, J. Circuits Syst. Comput..

A wirelessly powered system with charge recovery logic

Baris Taskin, Emre Salman, Leo Filippini, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

Process variation sensitivity of the Rotary Traveling Wave Oscillator

Baris Taskin, Ying Teng, 2011, 2011 12th International Symposium on Quality Electronic Design.

Wireless charge recovery system for implanted electroencephalography applications in mice

Baris Taskin, Lunal Khuon, Leo Filippini, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Leakage current analysis for intra-chip wireless interconnects

Baris Taskin, Ankit More, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Timing Optimization Through Clock Skew Scheduling

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2000 .

Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling

Baris Taskin, Shannon M. Kurtas, 2011, J. Circuits Syst. Comput..

Low Voltage Clock Tree Synthesis with Local Gate Clusters

Baris Taskin, Emre Salman, Can Sitik, 2019, ACM Great Lakes Symposium on VLSI.

Rotary traveling wave oscillator frequency division at nanoscale technologies

Baris Taskin, Ying Teng, 2013, GLSVLSI '13.

Linear timing analysis of SOC synchronous circuits with level-sensitive latches

Baris Taskin, Ivan S. Kourtev, 2002, 15th Annual IEEE International ASIC/SOC Conference.

EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs

Baris Taskin, Ankit More, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors

Baris Taskin, Scott Lerner, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Skew analysis and bounded skew constraint methodology for rotary clocking technology

Vinayak Honkote, Baris Taskin, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs

Baris Taskin, Ying Teng, Jianchao Lu, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks

Baris Taskin, Emre Salman, Can Sitik, 2015, ACM Great Lakes Symposium on VLSI.

Proceedings of the 20th System Level Interconnect Prediction Workshop

Baris Taskin, Tsung-Yi Ho, 2018, SLIP@DAC.

On-chip wireless interconnect paradigm

Baris Taskin, 2019, NoCArc@MICRO.

Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2002, TAU '02.

Low Frequency Rotary Traveling Wave Oscillators

Baris Taskin, Ragh Kuttappa, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Enhanced level shifter for multi-voltage operation

Baris Taskin, Emre Salman, Can Sitik, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC

Baris Taskin, Ankit More, 2010, 23rd IEEE International SOC Conference.

High-Performance, Low-Power Resonant Clocking: Embedded tutorial

Baris Taskin, Matthew R. Guthaus, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

From RTL to GDSII: An ASIC Design Course Development using Synopsys R

Baris Taskin, Jianchao Lu, 2011 .

Clock buffer polarity assignment considering capacitive load

Baris Taskin, Jianchao Lu, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Clock Skew Scheduling and Clock Tree Synthesis

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2009 .

ROA-brick topology for rotary resonant clocks

Baris Taskin, Ying Teng, Jianchao Lu, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Exploiting useful skew in gated low voltage clock trees

Baris Taskin, Emre Salman, Can Sitik, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Slew-down: analysis of slew relaxation for low-impact clock buffers

Baris Taskin, Scott Lerner, Eric Leggett, 2017, 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

A unified design methodology for a hybrid wireless 2-D NoC

Baris Taskin, Ankit More, 2012, 2012 IEEE International Symposium on Circuits and Systems.

3D NoCs with active interposer for multi-die systems

Baris Taskin, Vasil Pano, Ragh Kuttappa, 2019, NOCS.

Static thread mapping for NoCs via binary instrumentation traces

Baris Taskin, Ankit More, Mark Hempstead, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

Baris Taskin, Jianchao Lu, Yusuf Aksehir, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Post-CTS clock skew scheduling with limited delay buffering

Baris Taskin, Jianchao Lu, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

TSV Antennas for Multi-Band Wireless Communication

Baris Taskin, Vasil Pano, Yuqiao Liu, 2020, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

CROA: Design and Analysis of the Custom Rotary Oscillatory Array

Vinayak Honkote, Baris Taskin, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A shift-register-based QCA memory architecture

Baris Taskin, Andy Chiu, Jonathan Salkind, 2009, ACM J. Emerg. Technol. Comput. Syst..

Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis

Baris Taskin, Jianchao Lu, Xiaomi Mao, 2011, ISPD '11.

Iterative skew minimization for low swing clocks

Baris Taskin, Can Sitik, 2014, Integr..

Timing characterization of clock buffers for clock tree synthesis

Baris Taskin, Can Sitik, Scott Lerner, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

Proceedings of the 18th System Level Interconnect Prediction Workshop

Baris Taskin, Tsung-Yi Ho, 2016, SLIP.

RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer

Baris Taskin, Adarsha Balaji, Vasil Pano, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS

Baris Taskin, Scott Lerner, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Design Methodology for Voltage-Scaled Clock Distribution Networks

Baris Taskin, Emre Salman, Can Sitik, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs

Baris Taskin, Ankit More, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect

Baris Taskin, Ying Teng, 2010, J. Low Power Electron..

Advanced timing of level-sensitive sequential circuits

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Clock Tree Synthesis with XOR Gates for Polarity Assignment

Baris Taskin, Jianchao Lu, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

FOPAC: Flexible On-Chip Power and Clock

Baris Taskin, Selçuk Köse, Ragh Kuttappa, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A shift-register-based QCA memory architecture

Baris Taskin, Andy Chiu, Jonathan Salkind, 2007, 2007 IEEE International Symposium on Nanoscale Architectures.

SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads

Baris Taskin, Ankit More, Mark Hempstead, 2018, ACM Trans. Archit. Code Optim..

Zero clock skew synchronization with rotary clocking technology

Vinayak Honkote, Baris Taskin, 2009, 2009 10th International Symposium on Quality Electronic Design.

Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking

Baris Taskin, Bo Hong, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design and fabrication of two‐port three‐beam switched beam antenna array for 60 GHz communication

Baris Taskin, Yuqiao Liu, Kapil R. Dandekar, 2019, IET Microwaves, Antennas & Propagation.

Charge recovery implementation of an analog comparator: Initial results

Baris Taskin, Leo Filippini, Lunal Khuon, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Locality-Aware Network Utilization Balancing in NoCs

Baris Taskin, Ankit More, A. More, 2015, ACM Trans. Design Autom. Electr. Syst..

ADVANCED TIMING AND SYNCHRONIZATION METHODOLOGIES FOR DIGITAL VLSI INTEGRATED CIRCUITS

Baris Taskin, B. Taskin, 2005 .

NoC Router Lifetime Improvement using Per-Port Router Utilization

Baris Taskin, Vasil Pano, Scott Lerner, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects

Baris Taskin, Ankit More, 2010, GLSVLSI '10.

SLECTS: Slew-Driven Clock Tree Synthesis

Baris Taskin, Emre Salman, Savithri Sundareswaran, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low Swing — Low Frequency Rotary Traveling Wave Oscillators

Baris Taskin, Scott Lerner, Leo Filippini, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Synchronization scheme for brick-based rotary oscillator arrays

Baris Taskin, Ying Teng, 2012, GLSVLSI '12.

Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces

Baris Taskin, Mark Hempstead, Karthik Sangaiah, 2018, 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Custom topology rotary clock router with tree subnetworks

Baris Taskin, Joseph Demaio, Owen Farell, 2009, TODE.

Delay insertion method in clock skew scheduling

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors

Baris Taskin, Isikcan Yilmaz, Scott Lerner, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array

Vinayak Honkote, Baris Taskin, 2010, 2010 IEEE International Conference on Computer Design.

High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design

Baris Taskin, Emre Salman, Can Sitik, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Clock mesh synthesis with gated local trees and activity driven register clustering

Baris Taskin, Jianchao Lu, Xiaomi Mao, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation

Baris Taskin, Mark Hempstead, Scott Lerner, 2015, 2015 28th International Conference on VLSI Design.

Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis

Baris Taskin, Scott Lerner, 2018, 2018 Ninth International Green and Sustainable Computing Conference (IGSC).

FinFET-Based Low-Swing Clocking

Baris Taskin, Emre Salman, Can Sitik, 2015, ACM J. Emerg. Technol. Comput. Syst..

The Adiabatically Driven StrongARM Comparator

Baris Taskin, Leo Filippini, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

Innovative propagation mechanism for inter-chip and intra-chip communication

Baris Taskin, Damiano Patron, Vasil Pano, 2015, 2015 IEEE 16th Annual Wireless and Microwave Technology Conference (WAMICON).

From RTL to GDSII: An ASIC design course development using Synopsys® University Program

Baris Taskin, Jianchao Lu, 2011, 2011 IEEE International Conference on Microelectronic Systems Education.

Custom rotary clock router

Vinayak Honkote, Baris Taskin, 2008, 2008 IEEE International Conference on Computer Design.

Sparse-rotary oscillator array (SROA) design for power and skew reduction

Baris Taskin, Ying Teng, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design

Baris Taskin, Ying Teng, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Performance improvement of edge-triggered sequential circuits

Baris Taskin, Ivan S. Kourtev, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Scalable Resonant Power Clock Generation for Adiabatic Logic Design

Baris Taskin, Leo Filippini, Ragh Kuttappa, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Multiphase Digital Low-Dropout Regulators

Baris Taskin, Selçuk Köse, Ragh Kuttappa, 2022, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems

Baris Taskin, Vasil Pano, Scott Lerner, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Linearization of The Timing Analysis and Optimization of Level-Sensitive Circuits

Baris Taskin, B. Taskin, 2003 .

Wireless interconnects for inter-tier communication on 3D ICs

Baris Taskin, Ankit More, A. More, 2010, The 40th European Microwave Conference.

mm Wave Antenna Gain Switching to Mitigate Indoor Blockage

Baris Taskin, Kapil R. Dandekar, Ibrahim Tekin, 2018, 2018 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting.

In-package wireless communication with TSV-based antenna

Baris Taskin, Kapil R. Dandekar, Ibrahim Tekin, 2019 .