Ameya Bhide

A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices

Ameya Bhide, Atila Alvandpour, Dai Zhang, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators

Ameya Bhide, Atila Alvandpour, 2013, 2013 NORCHIP.

An 8-GS/s 200-MHz Bandwidth 68-mW $\Delta\Sigma$ DAC in 65-nm CMOS

Ameya Bhide, Atila Alvandpour, Behzad Mesgarzadeh, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Effect of Clock Duty-Cycle Error on Two-Channel Interleaved $\Delta\Sigma$ DACs

Ameya Bhide, Atila Alvandpour, Amin Ojani, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Ameya Bhide, 2015 .

A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-$\mu$m CMOS for Medical Implant Devices

Ameya Bhide, Atila Alvandpour, Dai Zhang, 2012, IEEE Journal of Solid-State Circuits.

A 1-GHz Bandwidth 12-bit SC DAC for 60-GHz Radio in 65-nm CMOS

Ameya Bhide, Quoc-Tai Duong, Atila Alvandpour, 2016 .

Timing challenges in high-speed interleaved ΔΣ DACs

Ameya Bhide, Atila Alvandpour, 2014, 2014 International Symposium on Integrated Circuits (ISIC).

Design and analysis of high-speed split-segmented switched-capacitor DACs

Ameya Bhide, Atila Alvandpour, Quoc-Tai Duong, 2017 .