Masanori Furuta

发表

C-12-21 A Settling-Time Analysis Model with the Secondary Pole in Amplifiers for Pipeline A/D Converters

Shoji Kawahito, Takeshi Takayama, Kazutaka Honda, 2005 .

Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits

Shoji Kawahito, Zheng Liu, Masanori Furuta, 2006, IEICE Trans. Electron..

A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues

Shoji Kawahito, Kazutaka Honda, Masanori Furuta, 2006, 2006 IEEE International Symposium on Circuits and Systems.

6.7 A 1.2e− temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA

Masanori Furuta, Yasuhiro Shinozuka, Tetsuro Itakura, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Calibration of Clock Skew and RC Mismatch in Time-Interleaved ADCs

Shoji Kawahito, Kazutaka Honda, Masanori Furuta, 2007 .

A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique

Masanori Furuta, Tetsuro Itakura, Mai Nozawa, 2011, IEEE Journal of Solid-State Circuits.

A digitally skew correctable multi-phase clock generator using a master-slave DLL

Shoji Kawahito, Atsushi Suzuki, Masanori Furuta, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC

Masanori Furuta, Daisuke Kurose, Tetsuro Itakura, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique (回路とシステム)

Masanori Furuta, Tetsuro Itakura, Taichi Ogawa, 2012 .

An area-efficient sampling rate converter using negative feedback technique

Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

Satoshi Kondo, Masanori Furuta, Tuan Thanh Ta, 2016, IEEE Journal of Solid-State Circuits.

A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

Shoji Kawahito, Masanori Furuta, Yukinari Nishikawa, 2007, 2007 IEEE Custom Integrated Circuits Conference.

A 1.0-V 12-bit Digitally Calibrated SAR ADC Using Hybrid Technique (集積回路)

Masanori Furuta, Tetsuro Itakura, Masazumi Shiochi, 2013 .

A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing

Akira Hyogo, Masanori Furuta, Tatsuji Matsuura, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters

Shoji Kawahito, Masanori Furuta, Daisuke Miyazaki, 2007, IEEE Transactions on Instrumentation and Measurement.

All-digital background calibration for time-interleaved ADC using pseudo aliasing signal

Masanori Furuta, Takafumi Yamaji, Tetsuro Itakura, 2012, 2012 IEEE International Symposium on Circuits and Systems.

All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal

Masanori Furuta, Takafumi Yamaji, Tetsuro Itakura, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Digital Calibration Technique of Capacitor Mismatch for Pipelined Analog-to-Digital Converters(Special Issue on High-Performance Analog Integrated Circuits)

Shoji Kawahito, Masanori Furuta, Daisuke Miyazaki, 2002 .

Converter using a Pseudo-Differential Architecture

Shoji Kawahito, Masanori Furuta, Daisuke Miyazaki, 2002 .

A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier

Ippei Akita, Masanori Furuta, Tetsuro Itakura, 2011, IEEE Asian Solid-State Circuits Conference 2011.

A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB

Masanori Furuta, Daisuke Kurose, Tetsuro Itakura, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Low-Power Design of High-Speed A/D Converters(Analog, Low-Power LSI and Low-Power IP)

Shoji Kawahito, Kazutaka Honda, Masanori Furuta, 2005 .

Amplifier, an electrical circuit, and an image sensor

Masanori Furuta, Yasuhiro Shinozuka, Kei Shiraishi, 2015 .

19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC

Satoshi Kondo, Masanori Furuta, Tuan Thanh Ta, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors

Masanori Furuta, Yasuhiro Shinozuka, Tetsuro Itakura, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

改善型12-bitカラム並列サイクリックA/D変換器を集積した広ダイナミックレンジCMOSイメージセンサ( イメージセンシング技術とその応用)

Shoji Kawahito, Masanori Furuta, Masaaki Sasaki, 2007 .

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS

Masanori Furuta, Shigehito Saigusa, Tetsuro Itakura, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Low-power design of high-speed A/D converters : Lower-power LSI and lower-power IP

Shoji Kawahito, Kazutaka Honda, Masanori Furuta, 2005 .

A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS

Ippei Akita, Masanori Furuta, Tetsuro Itakura, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Low-Power Design of High-Speed A/D Converters (INVITED)

Shoji Kawahito, Kazutaka Honda, Masanori Furuta, 2005 .

Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits

Hiroki Ishikuro, Masanori Furuta, Daisuke Kurose, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique

Masanori Furuta, Daisuke Kurose, Tetsuro Itakura, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Low-Power Design of High-Speed A/D Converters

Shoji Kawahito, Kazutaka Honda, Masanori Furuta, 2005, IEICE transactions on electronics.

A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS

Masanori Furuta, Tetsuro Itakura, Mai Nozawa, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS

Satoshi Kondo, Masanori Furuta, Tuan Thanh Ta, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier

Masanori Furuta, Tetsuro Itakura, Masahiro Hosoya, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

An Efficient Implementation of FPGA-based Object Detection Using Multi-scale Attention

Masanori Furuta, Koichiro Ban, Daisuke Kobayashi, 2021, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).