Chih-Tsun Huang

发表

A systematic approach to reducing semiconductor memory test time in mass production

Jen-Chieh Yeh, Cheng-Wen Wu, Shyr-Fen Kuo, 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults

Cheng-Wen Wu, Chih-Tsun Huang, Yen-Lin Peng, 2007, IET Comput. Digit. Tech..

Delay defect coverage for FPGA test configurations based on statistical evaluation

Cheng-Wen Wu, Chih-Tsun Huang, Yen-Lin Peng, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

A test access control and test integration system for system-on-chip

Cheng-Wen Wu, Chih-Tsun Huang, C.-W. Wang, 2002 .

Scalable Security Processor Design and Its Implementation

Cheng-Wen Wu, Chih-Tsun Huang, Chen-Hsing Wang, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

Simulation-based test algorithm generation for random access memories

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2000, Proceedings 18th IEEE VLSI Test Symposium.

On test and diagnostics of flash memories

Jen-Chieh Yeh, Yuan-Yuan Shih, Cheng-Wen Wu, 2004, 13th Asian Test Symposium.

Core-based system-on-chip testing: Challenges and opportunities

Chih-Tsun Huang, Cheng-Wen Wu, Jin-Fu Li, 2001 .

An SOC test integration platform and its industrial realization

Cheng-Wen Wu, Chih-Tsun Huang, Jing-Reng Huang, 2004 .

A High-Throughput Low-Power AES Cipher for Network Applications

Chih-Tsun Huang, Shin-Yi Lin, 2007, 2007 Asia and South Pacific Design Automation Conference.

Low-power embedded memory architecture design for SOC

Cheng-Wen Wu, Tian-Sheuan Chang, Chih-Tsun Huang, 2002 .

Error catch and analysis for semiconductor memories using March tests

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Soc Testing and Design for Testability

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Tsun Huang, 2006 .

An HMAC processor with integrated SHA-1 and MD5 algorithms

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Pin Su, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

An application-independent delay testing methodology for island-style FPGA

Cheng-Wen Wu, Chih-Tsun Huang, Yen-Lin Peng, 2004 .

iScan: Indirect-access scan test over HOY test platform

Shi-Yu Huang, Hsi-Pin Ma, Cheng-Wen Wu, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

DFT methodologies for a communications processor core

Chih-Tsun Huang, C.-P. Su, C.-W. Wu, 1998 .

Test scheduling and test access architecture optimization for system-on-chip

Youn-Long Lin, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques

Cheng-Wen Wu, Chih-Tsun Huang, Chun-Kai Hsu, 2008, 2008 17th Asian Test Symposium.

RAMSES: a fast memory fault simulator

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Flash memory built-in self-test using March-like algorithms

Jen-Chieh Yeh, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

ANetwork Security Processor Design Based onanIntegrated SOCDesign andTestPlatform

Shi-Yu Huang, Jen-Chieh Yeh, Cheng-Wen Wu, 2006 .

TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler

Yeh-Ching Chung, Chih-Tsun Huang, Jing-Jia Liou, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Real-Time Embedded Debug and Trace Platform for System-on-Chip

Chih-Tsun Huang, 顏廣愷, Guang-Kai Yen, 2009 .

Test and diagnosis of word-oriented multiport memories

Cheng-Wen Wu, Chih-Tsun Huang, Kuo-Liang Cheng, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

A network security processor design based on an integrated SOC design and test platform

Shi-Yu Huang, Jen-Chieh Yeh, Cheng-Wen Wu, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

A high-throughput low-cost AES processor

Cheng-Wen Wu, Chih-Tsun Huang, Tsung-Fu Lin, 2003, IEEE Communications Magazine.

Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications

Chih-Tsun Huang, Jyu-Yuan Lai, Chih-Tsun Huang, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

VLSI design of a high speed pipelined Reed-Solomon CODEC

Chih-Tsun Huang, C.-W. Wu, 1996 .

Design of low-cost elliptic curve cryptographic engines for ubiquitous security

Chih-Tsun Huang, Hsin-Yu Ting, Chih-Tsun Huang, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

A low-cost wireless interface with no external antenna and crystal oscillator for Cm-range contactless testing

Shi-Yu Huang, Hsi-Pin Ma, Cheng-Wen Wu, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

A Programmable BIST Core for Embedded DRAM

Cheng-Wen Wu, Chih-Tsun Huang, Jing-Reng Huang, 1999, IEEE Des. Test Comput..

Reliability analysis and improvement for multi-level non-volatile memories with soft information

Chih-Tsun Huang, Jian-Nan Chen, Shih-Liang Chen, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

March-based RAM diagnosis algorithms for stuck-at and coupling faults

Jin-Fu Li, Cheng-Wen Wu, Chih-Tsun Huang, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters

Shi-Yu Huang, Cheng-Wen Wu, Chih-Tsun Huang, 2001, Proceedings 10th Asian Test Symposium.

Fault simulation and test algorithm generation for random accessmemories

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test scheduling of BISTed memory cores for SoC

Youn-Long Lin, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Automatic generation of memory built-in self-test cores for system-on-chip

Jen-Chieh Yeh, Cheng-Wen Wu, Chih-Tsun Huang, 2001, Proceedings 10th Asian Test Symposium.

FAME: A Fault-Pattern Based Memory Failure Analysis Framework

Cheng-Wen Wu, Chih-Tsun Huang, Jih-Nung Lee, 2003, ICCAD 2003.

Built-in redundancy analysis for memory yield improvement

Jin-Fu Li, Cheng-Wen Wu, Chih-Tsun Huang, 2003, IEEE Trans. Reliab..

BRAINS: a BIST compiler for embedded memories

Ming-Chang Tsai, Cheng-Wen Wu, Chih-Tsun Huang, 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

FAME: A Fault-Pattern Based Memory Failure Analysis Framework

Cheng-Wen Wu, Chih-Tsun Huang, Jih-Nung Lee, 2003, ICCAD.

Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model

Chih-Tsun Huang, Jing-Jia Liou, Chi-Feng Wu, 2017, 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Application-level embedded communication tracer for many-core systems

Chih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, 2015, The 20th Asia and South Pacific Design Automation Conference.

A configurable AES processor for enhanced security

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Pin Su, 2005, ASP-DAC.

A configurable AES processor for enhanced security

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Pin Su, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Design and test of a scalable security processor

Cheng-Wen Wu, Chih-Tsun Huang, Chen-Hsing Wang, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

Shi-Yu Huang, Hsi-Pin Ma, Cheng-Wen Wu, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography

Chih-Tsun Huang, Jyu-Yuan Lai, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

TheHOY Tester-Can ICTesting GoWireless?

Chih-Tsun Huang, Po-Chiun Huang, Tsin-Yuan Chang, 2006 .

Optimization of Pattern Matching Circuits for Regular Expression on FPGA

Cheng-Hung Lin, Chih-Tsun Huang, Shih-Chieh Chang, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Program Committee

Michael S. Hsiao, Irith Pomeranz, Nur A. Touba, 2006, WOWMOM.

Fault pattern oriented defect diagnosis for memories

Hong-Tzer Yang, Cheng-Wen Wu, Chih-Tsun Huang, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures

Chih-Tsun Huang, Jing-Jia Liou, Ting-Shuo Hsu, 2013, MES '13.

AC-Plus Scan Methodology for Small Delay Testing and Characterization

Shi-Yu Huang, Hsi-Pin Ma, Cheng-Wen Wu, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Stable Performance MAC Protocol for HOY Wireless Tester under Large Population

Cheng-Wen Wu, Yu-Tsao Hsing, Chih-Tsun Huang, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Failure factor based yield enhancement for SRAM designs

Cheng-Wen Wu, Yu-Tsao Hsing, Chih-Tsun Huang, 2004 .

RAMSES-FT: a fault simulator for flash memory testing and diagnostics

Jen-Chieh Yeh, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

The HOY Tester-Can IC Testing Go Wireless?

Shi-Yu Huang, Cheng-Wen Wu, Yu-Tsao Hsing, 2006, 2006 International Symposium on VLSI Design, Automation and Test.

A programmable built-in self-test core for embedded memories

Cheng-Wen Wu, Chih-Tsun Huang, Jing-Reng Huang, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

An embedded infrastructure of debug and trace interface for the DSP platform

Chih-Tsun Huang, Ming-Chang Hsieh, 2008, 2008 45th ACM/IEEE Design Automation Conference.

A programmable built-in self-test core for embedded memories

Cheng-Wen Wu, Chih-Tsun Huang, Jing-Reng Huang, 2000, ASP-DAC.

Adaptive Power and Energy Management of the Symmetric Key Cryptographic Cores

Chih-Tsun Huang, Ping-Hua Hsieh, 謝萍華, 2009 .

An application-independent delay testing methodology for island-style FPGA

Cheng-Wen Wu, Chih-Tsun Huang, Yen-Lin Peng, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

Optimization of Regular Expression Pattern Matching Circuits on FPGA

Cheng-Hung Lin, Chih-Tsun Huang, Shih-Chieh Chang, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Single- and Multi-core Configurable AES Architectures for Flexible Security

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Pin Su, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High-speed C-testable systolic array design for Galois-field inversion

Cheng-Wen Wu, Chih-Tsun Huang, 1997, Proceedings European Design and Test Conference. ED & TC 97.

A high-throughput low-cost AES cipher chip

Cheng-Wen Wu, Chih-Tsun Huang, Tsung-Fu Lin, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators

Chih-Tsun Huang, Hao-Ning Wu, Chih-Tsun Huang, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Design of a scalable RSA and ECC crypto-processor

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Pin Su, 2003, ASP-DAC '03.

Design space exploration with a cycle-accurate systemC/TLM DRAM controller model

Chih-Tsun Huang, Jing-Jia Liou, Ting-Shuo Hsu, 2017, 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

高速率具可擴展性的 IPSec 處理器

Chih-Tsun Huang, 盧風其, Feng-Chi Lu, 2007 .

A word-based RSA crypto-processor with enhanced pipeline performance

Cheng-Wen Wu, Chih-Tsun Huang, Chen-Hsing Wang, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

A highly efficient AES cipher chip

Cheng-Wen Wu, Chih-Tsun Huang, Tsung-Fu Lin, 2003, ASP-DAC '03.

A Network Security Processor Design Based o na nIntegrate dSO CDesig nan dTes tPlatform

Shi-Yu Huang, Jen-Chieh Yeh, Cheng-Wen Wu, 2006 .

Failure factor based yield enhancement for SRAM designs

Cheng-Wen Wu, Yu-Tsao Hsing, Chih-Tsun Huang, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

High-performance architecture for Elliptic Curve Cryptography over binary field

Chih-Tsun Huang, Kai-Hsiang Yang, Jyu-Yuan Lai, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Simulation-based test algorithm generation and port scheduling for multi-port memories

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2001, DAC '01.

A BIST scheme for FPGA interconnect delay faults

Cheng-Wen Wu, Chun-Chieh Wang, Chih-Tsun Huang, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Design and test of a scalable security processor

Cheng-Wen Wu, Chih-Tsun Huang, Chen-Hsing Wang, 2005, ASP-DAC.

Diagonal test and diagnostic schemes for flash memories

Jen-Chieh Yeh, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings. International Test Conference.

An SOC test integration platform and its industrial realization

Chih-Tsun Huang, Jing-Reng Huang, Chih-Yen Lo, 2004, 2004 International Conferce on Test.

Design and analysis of a many-core processor architecture for multimedia applications

Chih-Tsun Huang, Jing-Jia Liou, Ting-Shuo Hsu, 2012, Proceedings of The 2012 Asia Pacific Signal and Information Processing Association Annual Summit and Conference.

Design of a scalable many-core processor for embedded applications

Chih-Tsun Huang, Jing-Jia Liou, Ting-Shuo Hsu, 2015, The 20th Asia and South Pacific Design Automation Conference.

Design and Evaluation of the Low-Density Parity-Check CODEC for Non-Volatile Memories

Chih-Tsun Huang, Bo-Ru Ke, 柯博儒, 2009 .

IoT: Source of test challenges

Mario Konijnenburg, Yervant Zorian, Erik Jan Marinissen, 2016, 2016 21th IEEE European Test Symposium (ETS).

A prototype of a wireless-based test system

Ying-Yen Chen, Hsi-Pin Ma, Cheng-Wen Wu, 2007, SoCC.

An HMAC processor with integrated SHA-1 and MD5 algorithms

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Pin Su, 2004 .

Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications

Chih-Tsun Huang, Liang-Chia Cheng, Jing-Jia Liou, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography

Chih-Tsun Huang, Jyu-Yuan Lai, Chih-Tsun Huang, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A true random generator design

Chih-Tsun Huang, Cheng-Wen Wu, C.-P. Su, 2002 .

Hardware/software co-designed accelerator for vector graphics applications

Yeh-Ching Chung, Chih-Tsun Huang, Yi-Cheng Chen, 2011, 2011 IEEE 9th Symposium on Application Specific Processors (SASP).

Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks

Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Design of a scalable RSA and ECC crypto-processor

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Pin Su, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

High-Performance Architecture for Elliptic Curve Cryptography over Prime Fields on FPGAs

Chih-Tsun Huang, Jyu-Yuan Lai, Chih-Tsun Huang, 2012 .