Fran Keyser

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

Thomas Toifl, Martin L. Schmatz, Michael Ruegg, 2010, IEEE Journal of Solid-State Circuits.

A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS

Thomas Toifl, Martin L. Schmatz, Michael Ruegg, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).