J. Nyathi

Clock skew tolerant communication scheme for SoC IP blocks

R.R. Rydberg, J. Nyathi, J. Delgado-Frias, 2008, 2008 51st Midwest Symposium on Circuits and Systems.

On nanoelectronic architectural challenges and solutions

U. Ruckert, V. Beiu, J. Nyathi, 2004, 4th IEEE Conference on Nanotechnology, 2004..

Bulk CMOS Device Optimization for High-Speed and Ultra-Low Power Operations

J. Nyathi, B. Bero, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Self-timed refreshing approach for dynamic memories

J.G. Delgado-Frias, J. Nyathi, 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).

A hybrid wave pipelined network router

José G. Delgado-Frias, J. Nyathi, J. Nyathi, 2002 .

High-performance parallel addition using hybrid wave-pipelining

J. Nyathi, J. Delgado-Frias, J. Levy, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

An experimental justification for the proportionality between the coherence bandwidth and the root mean square time delay spread using deterministic time of arrivals

J. Nyathi, S. Alhloul, U. Rogers, 2021, Phys. Commun..

A charge recycling differential noise immune perceptron

V. Beiu, J. Nyathi, S. Tatapudi, 2004, 2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541).