J. Beintner

On the retention time distribution of dual-channel vertical DRAM technologies

D. Casarotto, P. Poechmueller, J. Beintner, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies

J. Beintner, Y. Li, D. Chidambarrao, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Vertical pass transistor design for sub-100 nm DRAM technologies

E. Crabbe, W. Mueller, J. Beintner, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications

Y. Li, J. Beintner, D. Chidambarrao, 2004, IEEE Electron Device Letters.

FinFET SRAM for high-performance low-power applications

I. Aller, T. Ludwig, E. Nowak, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond

W. Bergner, W. Mueller, J. Beintner, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).