D. Chidambarrao

发表

On the retention time distribution of dual-channel vertical DRAM technologies

D. Casarotto, P. Poechmueller, J. Beintner, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies

J. Beintner, Y. Li, D. Chidambarrao, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

G. Burbach, D. Greenlaw, S.F. Huang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Technologies for scaling vertical transistor DRAM cells to 70 nm

C. Radens, R. Jammy, G. Bronner, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

Vertical pass transistor design for sub-100 nm DRAM technologies

E. Crabbe, W. Mueller, J. Beintner, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications

Y. Li, J. Beintner, D. Chidambarrao, 2004, IEEE Electron Device Letters.

(110) channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (Rext) engineering

S. Narasimha, E. Maciejewski, E. Leobandung, 2007, 2007 IEEE International Electron Devices Meeting.

Novel:: a nonlinear viscoelastic model for thermal oxidation of silicon

G. R. Srinivasan, D. Chidambarrao, G. Srinivasan, 1991 .

Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90 nm SOI ULSI Technology

S. Narasimha, D. Chidambarrao, D. Onsongo, 2005 .

Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure

C. Wann, D. Chidambarrao, J. Johnson, 2006, 2006 International Electron Devices Meeting.

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

D. Greenlaw, H.-J. Engelmann, N. Kepler, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Reduction of RTA-driven intra-die variation via model-based layout optimization

J.C. Scott, A. Mocuta, B. Goplen, 2006, 2009 Symposium on VLSI Technology.

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

J. Gill, D. Mocuta, D. Greenlaw, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Dual stress liner enhancement in hybrid orientation technology

M. Ieong, T. Kanarsky, D. Chidambarrao, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Strain effects on device characteristics: Implementation in drift-diffusion simulators

D. Chidambarrao, D. Chidambarrao, J. Egley, 1993 .

Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model

D. Chidambarrao, H. Wong, S. Laux, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Stresses in silicon substrates near isolation trenches

G. R. Srinivasan, D. Chidambarrao, G. Srinivasan, 1991 .

Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths

M. Ieong, Z. Ren, O. Dokumaci, 2005, 2005 IEEE International SOI Conference Proceedings.

Dislocation modeling for the silicon world

D. Chidambarrao, K. W. Schwarz, X. H Liu, 2001 .