K. McStay

发表

On the retention time distribution of dual-channel vertical DRAM technologies

D. Casarotto, P. Poechmueller, J. Beintner, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Scaling deep trench based eDRAM on SOI to 32nm and Beyond

K. McStay, G. Freeman, R. Krishnan, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies

J. Beintner, Y. Li, D. Chidambarrao, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

Technology-Model-Product Parallel Design for High Performance and Rapid Time to Market 65nm Technology-Generation Microprocessors

E. Crabbe, N. Zamdmer, K. McStay, 2007, 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications

J. Benedict, T. Kirihata, C. Norris, 2006, 2006 International Electron Devices Meeting.

Vertical pass transistor design for sub-100 nm DRAM technologies

E. Crabbe, W. Mueller, J. Beintner, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond

W. Bergner, W. Mueller, J. Beintner, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A highly manufacturable 110 nm DRAM technology with 8F/sup 2/ vertical transistor cell for 1Gb and beyond

W. Mueller, K. Varn, R. Jammy, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).