W. Bergner

On the retention time distribution of dual-channel vertical DRAM technologies

D. Casarotto, P. Poechmueller, J. Beintner, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

W/WN/poly gate implementation for sub-130 nm vertical cell DRAM

M. Naeem, A. Strong, G. Bronner, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Vertical pass transistor design for sub-100 nm DRAM technologies

E. Crabbe, W. Mueller, J. Beintner, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).