Maximilien Glorieux

发表

New D-Flip-Flop Design in 65 nm CMOS for Improved SEU and Low Power Overhead at System Level

Sylvain Clerc, Philippe Roche, Gilles Gasiot, 2013, IEEE Transactions on Nuclear Science.

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors

Dan Alexandrescu, Thomas Lange, Maksim Jenihhin, 2019, 2019 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

DAMSEL—Dynamic and Applicative Measurement of Single Events in Logic

Adrian Evans, Dan Alexandrescu, Kevin Sanchez, 2018, IEEE Transactions on Nuclear Science.

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

Dan Alexandrescu, Thomas Lange, Ludovica Bozzoli, 2018, 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

Single event multiple transient (SEMT) measurements in 65 nm bulk technology

Adrian Evans, Dan Alexandrescu, Véronique Ferlet-Cavrois, 2016, 2016 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

65 nm fault tolerant latch architecture based on transient propagation blocking

Sylvain Clerc, Philippe Roche, Gilles Gasiot, 2014, 2014 IEEE International Reliability Physics Symposium.

A call for cross-layer and cross-domain reliability analysis and management

Dan Alexandrescu, Enrico Costenaro, Maximilien Glorieux, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

EDA support for functional safety — How static and dynamic failure analysis can improve productivity in the assessment of functional safety

Adrian Evans, Dan Alexandrescu, Maximilien Glorieux, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques

Dan Alexandrescu, Luca Sterpone, Thomas Lange, 2019, 2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks – Supplemental Volume (DSN-S).

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Dan Alexandrescu, Luca Sterpone, Thomas Lange, 2019, 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Detailed SET Measurement and Characterization of a 65 nm Bulk Technology

Adrian Evans, Dan Alexandrescu, Sylvain Clerc, 2017, IEEE Transactions on Nuclear Science.

Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models

Dan Alexandrescu, Maximilien Glorieux, Aneesh Balakrishnan, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

Dan Alexandrescu, Luca Sterpone, Thomas Lange, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits

Sylvain Clerc, Philippe Roche, Jean-Luc Autran, 2014, Microelectron. Reliab..

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications

Dan Alexandrescu, Thomas Lange, Maksim Jenihhin, 2019, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects

Dan Alexandrescu, Thomas Lange, Maksim Jenihhin, 2020, 2020 9th Mediterranean Conference on Embedded Computing (MECO).

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features

Dan Alexandrescu, Luca Sterpone, Maximilien Glorieux, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis

Dan Alexandrescu, Maksim Jenihhin, Maximilien Glorieux, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).

Single-Event Characterization of Xilinx UltraScale+® MPSOC under Standard and Ultra-High Energy Heavy-Ion Irradiation

Dan Alexandrescu, Maria Kastriotou, Véronique Ferlet-Cavrois, 2018, 2018 IEEE Nuclear & Space Radiation Effects Conference (NSREC 2018).

Single Event Transient and TID Study in 28 nm UTBB FDSOI Technology

Li Chen, Richard Wong, Rui Liu, 2017, IEEE Transactions on Nuclear Science.

SER/SEL performances of SRAMs in UTBB FDSOI28 and comparisons with PDSOI and BULK counterparts

Cyril Bottoni, Philippe Roche, Dimitri Soussan, 2014, 2014 IEEE International Reliability Physics Symposium.

Experimental Soft Error Rate of Several Flip-Flop Designs Representative of Production Chip in 32 nm CMOS Technology

Sylvain Clerc, Fady Abouzeid, Philippe Roche, 2013, IEEE Transactions on Nuclear Science.