Kanwaldeep Sobti

The scan-DFT features of AMD's next-generation microprocessor core

Baosheng Wang, Grady Giles, Wei-Yu Chen, 2010, 2010 IEEE International Test Conference.

Accurate models for estimating area and power of FPGA implementations

Chaitali Chakrabarti, Kanwaldeep Sobti, Lanping Deng, 2008, 2008 IEEE International Conference on Acoustics, Speech and Signal Processing.

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Chaitali Chakrabarti, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Accurate Area, Time and Power Models for FPGA-Based Implementations

Chaitali Chakrabarti, Yuanrui Zhang, Kanwaldeep Sobti, 2011, J. Signal Process. Syst..

Structural tests of slave clock gating in low-power flip-flop

Jeff Rearick, Jayalakshmi Rajaraman, Kanwaldeep Sobti, 2011, 29th VLSI Test Symposium.

Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Chaitali Chakrabarti, 2006, 2006 IEEE International SOC Conference.

Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Chaitali Chakrabarti, 2007, 2007 IEEE Workshop on Signal Processing Systems.

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Chaitali Chakrabarti, 2009, IEEE Transactions on Computers.

Structural test of power-only defects: ATPG or ad-hoc?

Jeff Rearick, Grady Giles, Baosheng Wang, 2009, 2009 International Test Conference.