Raghavendra B. Deshmukh

发表

A Novel Parallel Multiplier for 2's Complement Numbers Using Booth's Recoding Algorithm

Chandrashekhar T. Kukade, Raghavendra B. Deshmukh, R. M. Patrikar, 2014, 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies.

Design of Low Power Parallel Multiplier

Raghavendra B. Deshmukh, Rahul M. Badghare, Sanjiv Kumar Mangal, 2009, J. Low Power Electron..

Overlap Aware Compressed Signal Classification

Raghavendra B. Deshmukh, Meenu Rani, Sanjay B. Dhok, 2020, IEEE Access.

FPGA Implementation of Low Power Parallel Multiplier

Raghavendra B. Deshmukh, Rahul M. Badghare, Sanjiv Kumar Mangal, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Powering Wireless Sensor Nodes using Ambient RF Energy

Raghavendra B. Deshmukh, Rajendra M. Patrikar, Shantanu A. Bhalerao, 2006, 2006 IEEE International Conference on Systems, Man and Cybernetics.

Hardware Implementation of Simeck Cipher as a Lightweight Hash Function

Raghavendra B. Deshmukh, Sanjay B. Dhok, Prachin Bhoyar, 2020 .

Data dependent spurious power reduction for fixed width multiplier

Raghavendra B. Deshmukh, Bharti Navlani, Pankaj U. Joshi, 2016, 2016 20th International Symposium on VLSI Design and Test (VDAT).

Real Time Mixing Index Measurement of Microchannels Using OpenCV

Raghavendra B. Deshmukh, Rajendra Patrikar, Khuushi, 2018, VDAT.

Dynamic capacitive sensing of droplet parameters in a low-cost open EWOD system

Raghavendra B. Deshmukh, Rajendra Patrikar, Vandana Jain, 2017 .

Design of resolution/power controllable Asynchronous Sigma-Delta Modulator

Raghavendra B. Deshmukh, Anita Arvind Deshmukh, 2016, EURASIP J. Adv. Signal Process..

Computational Functions' VLSI Implementation for Compressed Sensing

Raghavendra B. Deshmukh, Rajendra M. Patrikar, Shrirang Korde, 2013, VDAT.

A Machine Condition Monitoring Framework Using Compressed Signal Processing

Raghavendra B. Deshmukh, Meenu Rani, S. B. Dhok, 2020, Sensors.

Fast modular multiplication using parallel prefix adder

Raghavendra B. Deshmukh, Pravin P. Zode, 2014, 2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking.

Side channel attack resistant architecture for elliptic curve cryptography

Raghavendra B. Deshmukh, Pravin Zode, 2015, 2015 19th International Symposium on VLSI Design and Test.

Self-compensation scheme for truncation error in fixed width multipliers

Raghavendra B. Deshmukh, Pankaj U. Joshi, Venkateshwarlu Gudur, 2018, IET Circuits Devices Syst..

Low Power Asynchronous Sigma-Delta Modulator Using Hysteresis Level Control

Raghavendra B. Deshmukh, Rajendra M. Patrikar, Anita Arvind Deshmukh, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Side channel attack resistant architecture for elliptic curve cryptosystem

Raghavendra B. Deshmukh, Pravin Zode, 2018 .

Design and Fabrication of Versatile Low Power Wireless Sensor Nodes for IoT Applications

Raghavendra B. Deshmukh, Rajendra M. Patrikar, Saket Thool, 2018, VDAT.

Performance Analysis of Gated Ring Oscillator Designed for Audio Frequency Range Asynchronous ADC

Raghavendra B. Deshmukh, Anita Arvind Deshmukh, 2014 .

Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm

Raghavendra B. Deshmukh, Abdus Samad, Pravin Zode, 2017, VDAT.

MOS switch-based DPA-resistant GF(28) modulo multiplier

Raghavendra B. Deshmukh, Pravin Zode, 2018 .

Novel fault attack resistant architecture for elliptic curve cryptography

Raghavendra B. Deshmukh, Pravin Zode, 2021, Microprocess. Microsystems.

Wideband auto-tunable vibration energy harvester using change in centre of gravity

Raghavendra B. Deshmukh, R. Deshmukh, R. Somkuwar, 2018 .

Multi-band piezoelectric vibration energy harvester for low-frequency applications

Raghavendra B. Deshmukh, R. Deshmukh, R. Somkuwar, 2019, Microsystem Technologies.