Makoto Suwa

Substrate‐voltage control circuits for DRAMs at power‐on timing

Kenji Tokami, Michihiro Yamada, Hiroshi Miyamoto, 1992 .

Improved dynamic semiconductor memory device and method for an improved aging test of memory cells

Hiroshi Miyamoto, Shigeru Mori, Makoto Suwa, 1989 .

An efficient screening method for DRAM memory cell capacitor dielectric

Koichiro Mashiko, Michihiro Yamada, Kiyohiro Furutani, 1990 .

An adjustable output driver with self-recovering Vpp generator for 4 M/spl times/16 DRAM

Hiroshi Miyamoto, Yoshikazu Morooka, Kiyohiro Furutani, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Semiconductor memory device with test mode

Hiroshi Miyamoto, Makoto Suwa, 1991 .

A 45-ns 64-Mb DRAM with a merged match-line test architecture

S. Kayano, Michihiro Yamada, Tsutomu Yoshihara, 1991 .