Miriam Leeser

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Runtime assignment of reconfigurable hardware components for image processing pipelines

Heather M. Quinn, Laurie A. Smith King, Miriam Leeser, 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

A methodology for efficient hardware verification

Miriam Leeser, Mark Aagaard, M. Leeser, 1994, Formal Methods Syst. Des..

Vforce: An Extensible Framework for Reconfigurable

Miriam Leeser, Nicholas Moore, Albert Conti, 2007 .

Acknowledgment to special issue reviewers

David R. Kaeli, Miriam Leeser, 2008, J. Parallel Distributed Comput..

Stripmap SAR Pulse Interleaved Scheduling

Miriam Leeser, John Terragnoli, Paul Monticciolo, 2018, 2018 IEEE High Performance extreme Computing Conference (HPEC).

A data-centric approach to high-level synthesis

Miriam Leeser, Shantanu Tarafdar, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Precision Modeling and Bit-width Optimization of Floating-Point Applications

Miriam Leeser, Zhihong Zhao, 2003 .

An efficient implementation of a phase unwrapping kernel on reconfigurable hardware

Miriam Leeser, Sherman Braganza, M. Leeser, 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach

Miriam Leeser, Michaela Blott, Yaman Umuroglu, 2020, FPGA.

Fast reconstruction of 3D volumes from 2D CT projection data with GPUs

Miriam Leeser, Saoni Mukherjee, James Brock, 2014, BMC Research Notes.

Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic

Miriam Leeser, Joshua Noseworthy, 2006, FPGA '06.

Kernel Specialization Provides Adaptable GPU Code for Particle Image Velocimetry

Laurie A. Smith King, Miriam Leeser, Nicholas Moore, 2015, IEEE Transactions on Parallel and Distributed Systems.

Design issues for hardware implementation of an algorithm for segmenting hyperspectral imagery

James Theiler, Miriam Leeser, John J. Szymanski, 2000, SPIE Optics + Photonics.

Run-time execution of reconfigurable hardware in a Java environment

Demetris G. Galatopoullos, Elias S. Manolakos, Heather M. Quinn, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Applying reconfigurable hardware to the analysis of multispectral and hyperspectral imagery

Maya Gokhale, Pavle Belanovic, James Theiler, 2002, SPIE Optics + Photonics.

CUDA and OpenCL implementations of 3D CT reconstruction for biomedical imaging

Miriam Leeser, Nicholas Moore, Saoni Mukherjee, 2012, 2012 IEEE Conference on High Performance Extreme Computing.

High level synthesis for designing custom computing hardware

Miriam Leeser, Shantanu Tarafdar, Goran Doncev, 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

Implementing Murf: Accelerating Large State Space Exploration on FPGAs

Miriam Leeser, Mary Ellen Tie, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

Adaptable Two-Dimension Sliding Windows on NVIDIA GPUs with Runtime Compilation

Miriam Leeser, Nicholas Moore, Laurie Smith King, 2011, 2011 Symposium on Application Accelerators in High-Performance Computing.

Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA

Miriam Leeser, Marvin Onabajo, Peter Grossmann, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Enabling a real-time solution for neuron detection with reconfigurable hardware

Jennifer G. Dy, Miriam Leeser, Ben Cordes, 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

Verified high-level synthesis in BEDROC

Geoffrey Brown, Miriam Leeser, Richard Chapman, 1992, [1992] Proceedings The European Conference on Design Automation.

An FPGA Design Technique to Receive Multiple Wireless Protocols with the Same RF Front End

Miriam Leeser, Marvin Onabajo, Suranga Handagala, 2019, 2019 Wireless Days (WD).

The BEDROC high level synthesis system

Miriam Leeser, Mark Aagaard, Mark H. Linderman, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

A framework for specifying and designing pipelines

Miriam Leeser, Mark Aagaard, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Digital Pre-distortion Implemented Using FPGA

Ronan Farrell, Miriam Leeser, Sidath Madhuwantha, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

A Theorem Proving Based Methodology for Software Verification

Miriam Leeser, Mark Aagaard, 1993 .

Secure Function Evaluation Using an FPGA Overlay Architecture

Stratis Ioannidis, Xin Fang, Miriam Leeser, 2017, FPGA.

Memory traffic and data cache behavior of an MPEG-2 software decoder

Miriam Leeser, Peter Soderquist, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

Session details: Session: Applications I

Miriam Leeser, 2020 .

Field-Programmable Gate Arrays in Embedded Systems

Russell Tessier, Miriam Leeser, Scott Hauck, 2006, EURASIP Journal on Embedded Systems.

A Framework for Developing Parallel Applications with high level Tasks on Heterogeneous Platforms

Chao Liu, Miriam Leeser, 2017, PMAM@PPoPP.

FPGA-based hyperspectral covariance coprocessor for size, weight, and power constrained platforms

Miriam Leeser, David A. Kusinsky, 2013, 2013 IEEE High Performance Extreme Computing Conference (HPEC).

Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification

Miriam Leeser, Mark Aagaard, M. Leeser, 1995, IEEE Trans. Software Eng..

A Petri-Net Based Pre-Runtime Scheduler for Dynamically Self-Reconfiguration of FPGAs

Kia Bazargan, Jennifer G. Dy, Manoel Eusebio de Lima, 2005 .

Vforce: An Extensible Framework for Reconfigurable Supercomputing

Laurie A. Smith King, Miriam Leeser, Nicholas Moore, 2007, Computer.

Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency

Miriam Leeser, Peter Soderquist, Juan Carlos Rojas, 2006, IEEE Transactions on Multimedia.

Toward a Super Duper Hardware Tactic

Miriam Leeser, Mark Aagaard, Phillip J. Windley, 1993, HUG.

An FPGA Implementation of Explicit-State Model Checking

Miriam Leeser, Tim Leonard, Mary Ellen Fuess, 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.

Hardware-Software Codesign of Wireless Transceivers on Zynq Heterogeneous Systems

Miriam Leeser, Tuan Dao, Benjamin Drozdenko, 2018, IEEE Transactions on Emerging Topics in Computing.

Spatial and color clustering on an FPGA-based computer system

Miriam Leeser, Natalya V. Kitaryeva, Jill D. Crisman, 1998, Other Conferences.

K-means Clustering for Multispectral Images Using Floating-Point Divide

Miriam Leeser, Xiaojun Wang, 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

HML, a novel hardware description language and its translation to VHDL

Miriam Leeser, Yanbing Li, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Minimum energy operation for clustered island-style FPGAs

Miriam Leeser, Marvin Onabajo, Peter Grossmann, 2013, FPGA '13.

VForce: An environment for portable applications on high performance systems with accelerators

Laurie A. Smith King, Miriam Leeser, Nicholas Moore, 2012, J. Parallel Distributed Comput..

Efficient template matching with variable size templates in CUDA

Laurie A. Smith King, Miriam Leeser, Nicholas Moore, 2010, 2010 IEEE 8th Symposium on Application Specific Processors (SASP).

Erratum to: High level synthesis and generation FPGAs with the BEDROC system

Miriam Leeser, 1993, J. VLSI Signal Process..

Design and analysis of a dynamically reconfigurable three-dimensional FPGA : Reconfigurable and Adaptive VLSI Systems

Miriam Leeser, M. Michael Vai, Silviu Chiricescu, 2001 .

PBS: proven Boolean simplification

Miriam Leeser, Mark Aagaard, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An Automaton Model for Scheduling Constraints in Synchronous Machines

Wayne H. Wolf, Miriam Leeser, Andrés Takach, 1995, IEEE Trans. Computers.

Kernel Specialization for Improved Adaptability and Performance on Graphics Processing Units (GPUs)

Laurie A. Smith King, Miriam Leeser, Nicholas Moore, 2013, 2013 IEEE 27th International Symposium on Parallel and Distributed Processing.

Programming portable optimized multimedia applications

Miriam Leeser, Juan Carlos Rojas, 2003, MULTIMEDIA '03.

Development of a low-cost, adaptive, clinician-friendly virtual rehabilitation system

Miriam Leeser, Dagmar Sternad, Meghan E. Huber, 2013, 2013 International Conference on Virtual Rehabilitation (ICVR).

Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging

Eric L. Miller, Miriam Leeser, Srdjan Coric, 2002, FPGA '02.

Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs

Xin Fang, Miriam Leeser, M. Leeser, 2016, ACM Trans. Reconfigurable Technol. Syst..

3D CNN Acceleration on FPGA using Hardware-Aware Pruning

Massoud Pedram, Miriam Leeser, Xue Lin, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Efficient Shallow Water Simulations on GPUs

Miriam Leeser, Nicholas Moore, Laurie Smith King, 2011 .

Cardiac MRI compressed sensing image reconstruction with a graphics processing unit

Miriam Leeser, Martin Uecker, Majid Sabbagh, 2016, 2016 10th International Symposium on Medical Information and Communication Technology (ISMICT).

FPGA modeling techniques for detecting and demodulating multiple wireless protocols

Miriam Leeser, Kaushik R. Chowdhury, Suranga Handagala, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Hardware Specification, Verification and Synthesis: Mathematical Aspects

Geoffrey Brown, Miriam Leeser, 1990, Lecture Notes in Computer Science.

Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware

Laurie A. Smith King, Miriam Leeser, Nicholas Moore, 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

Balance power leakage to fight against side-channel analysis at gate level in FPGAs

Xin Fang, Miriam Leeser, Yunsi Fei, 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Rothko: A Three-Dimensional FPGA

Weidong Xu, Miriam Leeser, Waleed Meleis, 1998, IEEE Des. Test Comput..

A Library of Parameterized Floating-Point Modules and Their Use

Pavle Belanovic, Miriam Leeser, 2002, FPL.

Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware

Jennifer G. Dy, Miriam Leeser, Ben Cordes, 2005, IEEE International Workshop on Rapid System Prototyping.

Session details: Applications I

Miriam Leeser, 2013, FPGA '13.

Dynamo: A Runtime Partitioning System

Heather M. Quinn, Laurie A. Smith King, Miriam Leeser, 2004, ERSA.

Validity and reliability of kinect for measuring shoulder joint angles

Miriam Leeser, Dagmar Sternad, Meghan E. Huber, 2014, 2014 40th Annual Northeast Bioengineering Conference (NEBEC).

Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA

David R. Kaeli, Miriam Leeser, Perhaad Mistry, 2009, GPGPU-2.

Performance prediction techniques for scalable large data processing in distributed MPI systems

Miriam Leeser, Ningfang Mi, Janki Bhimani, 2016, 2016 IEEE 35th International Performance Computing and Communications Conference (IPCCC).

Division and square root: choosing the right implementation

Miriam Leeser, Peter Soderquist, M. Leeser, 1997, IEEE Micro.

Wave-based modeling, highlighting underground sensing and imaging

Miriam Leeser, Carey M. Rappaport, Sara Wadia-Fascetti, 2006 .

Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization

Jason Hickey, Miriam Leeser, Mark Aagaard, 1994, TPCD.

Side-channel analysis of MAC-Keccak hardware implementations

David R. Kaeli, Xin Fang, Miriam Leeser, 2015, HASP@ISCA.

Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware

Miriam Leeser, Nicholas Moore, Albert Conti, 2007 .

FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms

Miriam Leeser, Vinay Sriram, M. Leeser, 2009, EURASIP J. Embed. Syst..

Cognitive radio universal software hardware

Miriam Leeser, Kaushik R. Chowdhury, George Eichinger, 2012, 2012 IEEE International Symposium on Dynamic Spectrum Access Networks.

Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic

Miriam Leeser, Kenneth O'Brien, Thomas B. Preußer, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Using High Level GPU Tasks to Explore Memory and Communications Options on Heterogeneous Platforms

Chao Liu, Miriam Leeser, Janki Bhimani, 2017, SEM4HPC@HPDC.

High level synthesis and generating FPGAs with the BEDROC system

Miriam Leeser, Mark Aagaard, Mark H. Linderman, 1993, J. VLSI Signal Process..

Integrating floorplanning in data-transfer based high-level synthesis

Miriam Leeser, Shantanu Tarafdar, Zixin Yin, 1998, ICCAD.

Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation

Miriam Leeser, Scott Bailie, 2012, FPGA '12.

Design space exploration of GPU Accelerated cluster systems for optimal data transfer using PCIe bus

Miriam Leeser, Ningfang Mi, Janki Bhimani, 2016, 2016 IEEE High Performance Extreme Computing Conference (HPEC).

Architectural design of a three dimensional FPGA

Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.

Accelerating a MATLAB Application with Nvidia GPUs: a Case Study for GPU Library Construction

Miriam Leeser, Nicholas Moore, 2009 .

FIM: Performance Prediction for Parallel Computation in Iterative Data Processing Applications

Miriam Leeser, Ningfang Mi, Zhengyu Yang, 2017, 2017 IEEE 10th International Conference on Cloud Computing (CLOUD).

A Library of Parameterized Hardware Modules for Floating Point Arithmetic and Its Use

Pavle Belanovic, Miriam Leeser, 2002 .

Implementing a MATLAB-Based Self-configurable Software Defined Radio Transceiver

Subramanian Ramanathan, Miriam Leeser, Kaushik R. Chowdhury, 2015, CrownCom.

Design and analysis of a dynamically reconfigurable three-dimensional FPGA

Miriam Leeser, Mankuan Michael Vai, Silviu M. S. A. Chiricescu, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units

David Kaeli, Miriam Leeser, 2009 .

Truly rapid prototyping requires high level synthesis

Miriam Leeser, Shantanu Tarafdar, Goran Doncev, 1998, Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237).

HML: an innovative hardware description language and its translation to VHDL

Miriam Leeser, Yanbing Li, Yanbing Li, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

Special issue: General-purpose processing using graphics processing units

Miriam Leeser, David R. Kaeli, M. Leeser, 2008, J. Parallel Distributed Comput..

An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs

Miriam Leeser, Jainik Kathiara, 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

Reasoning About Pipelines with Structural Hazards

Miriam Leeser, Mark Aagaard, 1994, TPCD.

EDISYN: A Language-Based Editor for High-level Synthesis

Geoffrey Brown, Miriam Leeser, Chee-Keng Chang, 1991 .

Accelerating Algorithms on GPUs in SCIRun: the Conjugate Gradient Case Study

Dana H. Brooks, Miriam Leeser, Devon Yablonski, 2011 .

Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware

James Theiler, Miriam Leeser, John J. Szymanski, 2001, FPGA '01.

Dynamo: A Runtime Codesign Environment

Miriam Leeser, Heather Quinn, L. A. Smith-King, 2004 .

Strategies and Demonstration to Support Multiple Wireless Protocols with a Single RF Front-End

Mohamed Mohamed, Miriam Leeser, Marvin Onabajo, 2020, IEEE Wireless Communications.

A Novel Physical Layer Authentication With PAPR Reduction Based on Channel and Hardware Frequency Responses

David Malone, Ronan Farrell, Miriam Leeser, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

PARAMETERIZED K-MEANS CLUSTERING FOR RAPID HARDWARE DEVELOPMENT TO ACCELERATE ANALYSIS OF SATELLITE DATA

Maya Gokhale, James Theiler, Miriam Leeser, 2001 .

GPGPU Computing for Cloud Auditing

Miriam Leeser, Virginia W. Ross, 2014 .

The DT-model: high-level synthesis using data transfers

Miriam Leeser, Shantanu Tarafdar, M. Leeser, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2009, Washington, DC, USA, March 8, 2009

David Kaeli, Miriam Leeser, M. Leeser, 2009, General Purpose Processing on Graphics Processing Units.

Implementing Filters with programmable logic

Miriam Leeser, Richard Chapman, Michael Bertone, 1994 .

Rapid prototyping of datapath intensive architectures with HML: an abstract hardware description language

Miriam Leeser, Yanbing Li, Shantanu Tarafdar, 1996, Other Conferences.

High-Level and Compact Design of Cross-Channel LTE DownLink Channel Encoder

Miriam Leeser, Jieming Xu, 2018, CrownCom.

Verification of a subtractive radix-2 square root algorithm and implementation

Miriam Leeser, John W. O'Leary, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach

Linda Doyle, Miriam Leeser, Michaela Blott, 2020, IEEE Transactions on Computers.

Vendor agnostic, high performance, double precision Floating Point division for FPGAs

Xin Fang, Miriam Leeser, 2013, 2013 IEEE High Performance Extreme Computing Conference (HPEC).

SIFO: Secure Computational Infrastructure using FPGA Overlays pdf

Stratis Ioannidis, Miriam Leeser, Xin Fang, 2019, Int. J. Reconfigurable Comput..

Digital Logic

Miriam Leeser, James Brock, 2014, Computing Handbook, 3rd ed..

Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework

Miriam Leeser, Kaushik R. Chowdhury, Jonathon Pendlum, 2014, FCCM 2014.

Field Programmable Gate Arrays

Miriam Leeser, 2008 .

Advanced Components in the Variable Precision Floating-Point Library

Miriam Leeser, Xiaojun Wang, Sherman Braganza, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Area and performance tradeoffs in floating-point divide and square-root implementations

Miriam Leeser, Peter Soderquist, M. Leeser, 1996, CSUR.

Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency

Miriam Leeser, Peter Soderquist, M. Leeser, 1999, IEEE Transactions on Multimedia.

Real Time Receiver Baseband Processing Platform for Sub 6 GHz PHY Layer Experiments

Miriam Leeser, Suranga Handagala, 2020, IEEE Access.

GPU Acceleration in a Modern Problem Solving Environment: SCIRun's Linear System Solvers

Dana H. Brooks, Miriam Leeser, Devon Yablonski, 2004 .

Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects

Geoffrey Brown, Miriam Leeser, 1989 .

Garbled Circuits in the Cloud using FPGA Enabled Nodes

Stratis Ioannidis, Miriam Leeser, Kai Huang, 2019, 2019 IEEE High Performance Extreme Computing Conference (HPEC).

Simulation of digital circuits in the presence of uncertainty

Miriam Leeser, Mark H. Linderman, 1994, ICCAD '94.

Behavioral Non-portability in Scientific Numeric Computing

Miriam Leeser, Mahsa Bayati, Thomas Wahl, 2015, Euro-Par.

From Programs to Transistors: Verifying Hardware Synthesis Tools

Miriam Leeser, Geoffrey M. Brown, M. Leeser, 1989, Hardware Specification, Verification and Synthesis.

An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware

Miriam Leeser, S. Braganza, 2008, FCCM.

Automatic determination of signal flow through MOS transistor networks

W. F. Clocksin, Miriam Leeser, W. Clocksin, 1986, Integr..

VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware

Miriam Leeser, Xiaojun Wang, 2010, TRETS.

OpenCL Floating Point Software on Heterogeneous Architectures – Portable or Not?

Miriam Leeser, Thomas Wahl, Devon Yablonski, 2012 .

Accelerating big data applications using lightweight virtualization framework on enterprise cloud

Miriam Leeser, Ningfang Mi, Zhengyu Yang, 2017, 2017 IEEE High Performance Extreme Computing Conference (HPEC).

Local and Global Shared Memory for Task Based HPC Applications on Heterogeneous Platforms

Chao Liu, Miriam Leeser, 2018, 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP).

Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA

Miriam Leeser, Joshua Noseworthy, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Adaptive motor control with reconfigurable logic

Miriam Leeser, Karen Matulis, 1999, Optics East.

Optimizing the data cache performance of a software MPEG-2 video decoder

Miriam Leeser, Peter Soderquist, 1997, MULTIMEDIA '97.

A prototype FPGA for subthreshold-optimized CMOS (abstract only)

Miriam Leeser, Peter Grossmann, 2011, FPGA '11.

Make it real: Effective floating-point reasoning via exact arithmetic

Miriam Leeser, Thomas Wahl, Saoni Mukherjee, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Efficient FPGA implementation of qr decomposition using a systolic array architecture

Miriam Leeser, Xiaojun Wang, 2008, FPGA '08.

Implementing a RAKE receiver for wireless communications on an FPGA-based computer system

Miriam Leeser, Ali M. Shankiti, 2000, FPGA '00.

Reasoning about the function and timing of integrated circuits with interval temporal logic

Miriam Leeser, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

K-means Clustering for Multispectral Images Using Floating-Point Divide

Miriam Leeser, Xiaojun Wang, M. Leeser, 2007 .

Cache-sensitive architectural optimizations for mpeg-2 video decoding

Miriam Leeser, Peter Soderquist, 1998 .

A formally verified system for logic synthesis

Miriam Leeser, Mark Aagaard, M. Leeser, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware

Miriam Leeser, Gilead Tadmor, Abderrahmane Bennis, 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.

New Performance Modeling Methods for Parallel Data Processing Applications

Miriam Leeser, Ningfang Mi, Zhengyu Yang, 2019, TOMC.

An area/performance comparison of subtractive and multiplicative divide/square root implementations

Miriam Leeser, Peter Soderquist, M. Leeser, 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

The challenges of writing portable, correct and high performance libraries for GPUs

Dana H. Brooks, Laurie A. Smith King, Miriam Leeser, 2011, CARN.

Precision Modeling of Floating-Point Applications for Variable Bitwidth Computing

Miriam Leeser, Zhihong Zhao, M. Leeser, 2003, Engineering of Reconfigurable Systems and Algorithms.

Unified and lightweight tasks and conduits: A high level parallel programming framework

Chao Liu, Miriam Leeser, M. Leeser, 2016, 2016 IEEE High Performance Extreme Computing Conference (HPEC).

Detection of Different Wireless Protocols on an FPGA with the Same Analog/RF Front End

Miriam Leeser, Marvin Onabajo, Suranga Handagala, 2018, CrownCom.

Accelerating Large Garbled Circuits on an FPGA-enabled Cloud

Miriam Leeser, Stratis Ioannidis, Kai Huang, 2019, 2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).

Smart camera based on reconfigurable hardware enables diverse real-time applications

Miriam Leeser, Haiqian Yu, Shawn Miller, 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework

Miriam Leeser, Kaushik R. Chowdhury, Jonathon Pendlum, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

High-Level System Design of IEEE 802.11b Standard-Compliant Link Layer for MATLAB-Based SDR

Subramanian Ramanathan, Miriam Leeser, Kaushik R. Chowdhury, 2016, IEEE Access.

GPU implementation of reverse coordinate conversion for proteins

Jaydeep P. Bardhan, Miriam Leeser, Mahsa Bayati, 2015, 2015 IEEE High Performance Extreme Computing Conference (HPEC).

Real-Time Particle Image Velocimetry for Feedback Loops Using FPGA Implementation

Miriam Leeser, Gilead Tadmor, Stefan Siegel, 2005 .

Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units

David Kaeli, Miriam Leeser, 2010 .

QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware

Linda Doyle, Miriam Leeser, Michaela Blott, 2019, ACM J. Emerg. Technol. Comput. Syst..

Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification

Miriam Leeser, Mark Aagaard, M. Leeser, 1992, CAV.

Force: An extensible framework for configurable sup ercomputing

Miriam Leeser, Nicholas Moore, Albert Conti, 2007 .

High-level hardware-software co-design of an 802.11a transceiver system using Zynq SoC

Miriam Leeser, Kaushik R. Chowdhury, Tuan Dao, 2016, 2016 IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS).

Power analysis attack on hardware implementation of MAC-Keccak on FPGAs

David R. Kaeli, Xin Fang, Miriam Leeser, 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2010, Pittsburgh, Pennsylvania, USA, March 14, 2010

David Kaeli, Miriam Leeser, 2010, GPGPU.

Real-Time Particle Image Velocimetry for Feedback Loops Using FPGA Implementation

Miriam Leeser, Gilead Tadmor, Stefan Siegel, 2005, J. Aerosp. Comput. Inf. Commun..

Simulation Of Digital Circuits In The Presence of Uncertainty

Miriam Leeser, Mark H. Linderman, 1994, IEEE/ACM International Conference on Computer-Aided Design.

An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm

Wang Chen, Miriam Leeser, Carey M. Rappaport, 2004, FPGA '04.

Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems

Heather M. Quinn, Laurie A. Smith King, Miriam Leeser, 2007, Journal of Real-Time Image Processing.

Reasoning about the function and timing of integrated circuits with Prolog and temporal logic

Miriam Leeser, 1987 .

CHOOSING THE RIGHT IMPLEMENTATION

Miriam Leeser, Peter Soderquist, 1997 .

Leakage evaluation on power balance countermeasure against side-channel attack on FPGAs

Xin Fang, Miriam Leeser, Yunsi Fei, 2015, 2015 IEEE High Performance Extreme Computing Conference (HPEC).

Improving the performance of parallel backprojection on a reconfigurable supercomputer

Eric L. Miller, Miriam Leeser, Richard W. Linderman, 2006, SC.

The Implementation and Proof of a Boolean Simplification System

Miriam Leeser, Mark Aagaard, 1991 .

The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware

Miriam Leeser, Sherman Braganza, M. Leeser, 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).

A Methodology for Reusable Hardware Proofs

Miriam Leeser, Mark Aagaard, 1992, TPHOLs.

Automatic Sliding Window Operation Optimization for FPGA-Based

Miriam Leeser, Haiqian Yu, 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

The Effect of Parameterization on a Reconfigurable Implementation of PIV

Miriam Leeser, Gilead Tadmor, Abderrahmane Bennis, 2009, ERSA.

Multimedia Macros for Portable Optimized Programs

Miriam Leeser, Juan Carlos Rojas, 2004 .

Accelerating K-Means clustering with parallel implementations and GPU computing

Miriam Leeser, Ningfang Mi, Janki Bhimani, 2015, 2015 IEEE High Performance Extreme Computing Conference (HPEC).

Dynamic Deployment of Communication Applications to Different Hardware Platforms using Ontological Representations

Mieczyslaw M. Kokar, Miriam Leeser, Shweta Singh, 2018, 2018 IEEE High Performance extreme Computing Conference (HPEC).

Accuracy of kinect for measuring shoulder joint angles in multiple planes of motion

Miriam Leeser, Dagmar Sternad, Amee L. Seitz, 2015, 2015 International Conference on Virtual Rehabilitation (ICVR).

Identifying volatile numeric expressions in numeric computing applications

Miriam Leeser, Mahsa Bayati, Thomas Wahl, 2019, Math. Comput. Simul..

A truly two-dimensional systolic array FPGA implementation of QR decomposition

Miriam Leeser, Xiaojun Wang, 2009, TECS.

Cognitive radio universal software hardware

Miriam Leeser, Kaushik R. Chowdhury, George Eichinger, 2012, DySPAN.

Rothko: A three dimensional FPGA architecture, its fabrication, and design tools

Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, 1997, FPL.

Cross Component Optimization for Modern LTE Downlink Shared Channel Implementation

Miriam Leeser, Jieming Xu, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers

Miriam Leeser, Kaushik R. Chowdhury, Tuan Dao, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

HML: A Hardware Description Language Based on Standard ML

Miriam Leeser, Mark Aagaard, Mark H. Linderman, 1993, CHDL.

State-Action Based Link Layer Design for IEEE 802.11b Compliant MATLAB-Based SDR

Subramanian Ramanathan, Miriam Leeser, Kaushik R. Chowdhury, 2016, 2016 International Conference on Distributed Computing in Sensor Systems (DCOSS).

Accelerating protein coordinate conversion using GPUs

Jaydeep P. Bardhan, Miriam Leeser, Mahsa Bayati, 2014, 2014 IEEE High Performance Extreme Computing Conference (HPEC).

Finite Difference Time Domain: A Case Study Using FPGAs

Miriam Leeser, Wang Chen, 2008 .

Session details: Special Issue: HEART '15

Martin C. Herbordt, Miriam Leeser, 2016 .

High‐performance transformation of protein structure representation from internal to Cartesian coordinates

Miriam Leeser, Mahsa Bayati, Jaydeep P Bardhan, 2020, J. Comput. Chem..

Parallel Backprojection: A Case Study in High-Performance Reconfigurable Computing

Miriam Leeser, Ben Cordes, M. Leeser, 2009, EURASIP J. Embed. Syst..

Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging

Eric L. Miller, Miriam Leeser, Srdjan Coric, 2005, J. VLSI Signal Process..

The Open Cloud Testbed (OCT): A Platform for Research into new Cloud Technologies

Peter Desnoyers, Michael Zink, Miriam Leeser, 2021, 2021 IEEE 10th International Conference on Cloud Networking (CloudNet).

Evaluating Theoretical Baselines for ML Benchmarking Across Different Accelerators

Linda Doyle, Miriam Leeser, Michaela Blott, 2021 .

FPGAs in the Cloud

Volodymyr Kindratenko, Michael Zink, Miriam Leeser, 2021, Computing in Science & Engineering.

Accelerating Matrix Processing for MIMO Systems

Miriam Leeser, Jieming Xu, 2021, HEART.

K-means Parallelism on FPGA

Mieczyslaw M. Kokar, Thomas C. Sheahan, Miriam Leeser, 2018 .

Phase unwrapping using reconfigurable hardware

Miriam Leeser, C. A. DiMarzio, W. C. Warger, 2006 .

Variable Precision Floating Point Division and Square Root

Miriam Leeser, Xiaojun Wang, 2005 .

The effect of temporal impulse response on experimental reduction of photon scatter in time-resolved diffuse optical tomography.

Miriam Leeser, Mark Niedre, Niksa Valim, 2013, Physics in medicine and biology.

Using Nuprl for the verification and synthesis of hardware

Miriam Leeser, 1992, Philosophical Transactions of the Royal Society of London. Series A: Physical and Engineering Sciences.

Adapting the USRP as an Underwater Acoustic Modem

Milica Stojanovic, Paul Ozog, Miriam Leeser, 2009 .