Dilip P. Vasudevan

发表

Ultra Low Power Asynchronous Charge Sharing Logic

Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens, 2012, J. Low Power Electron..

A New Reversible Logic Gate and its Applications

Parag K. Lala, Dilip P. Vasudevan, 2004, ESA/VLSI.

Logic implementation using a reversible gate

Parag K. Lala, James Patrick Parkerson, Dilip P. Vasudevan, 2004, Circuits, Signals, and Systems.

A novel approach for on-line testable reversible logic circuit design

Parag K. Lala, James Patrick Parkerson, Dilip P. Vasudevan, 2004, 13th Asian Test Symposium.

Online testable reversible logic circuit design using NAND blocks

Parag K. Lala, James Patrick Parkerson, Dilip P. Vasudevan, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

A 6.45 $\mu{\rm W}$ Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems

Xing Chen, David D. Wentzloff, Benton H. Calhoun, 2015, IEEE Transactions on Biomedical Circuits and Systems.

PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments

John Shalf, David Donofrio, George Michelogiannakis, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture

Andrew A. Chien, Tung Thanh Hoang, Amirali Shambayati, 2015, CARN.

Synthesis of nanoelectronic circuits on delay-insensitive cellular arrays

Jia Di, Dilip P. Vasudevan, 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding

Parag K. Lala, James Patrick Parkerson, Dilip P. Vasudevan, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Partial Scan Based Test Generation for Asynchronous Circuits

Aristides Efthymiou, Dilip P. Vasudevan, A. Efthymiou, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data

Andrew A. Chien, Dilip P. Vasudevan, 2015, ACM Great Lakes Symposium on VLSI.

Ultra Low Power Booth Multiplier Using Asynchronous Logic

Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens, 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder

Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens, 2011, 2011 14th Euromicro Conference on Digital System Design.

Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies

John Shalf, David Donofrio, George Michelogiannakis, 2017, ISC Workshops.

Reversible-logic design with online testability

Parag K. Lala, Dilip P. Vasudevan, Jia Di, 2006, IEEE Transactions on Instrumentation and Measurement.

A technique for modular design of self-checking carry-select adder

Parag K. Lala, Dilip P. Vasudevan, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

On the effect of stuck-at faults on delay-insensitive nanoscale circuits

Jia Di, Parag K. Lala, Dilip P. Vasudevan, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing

Hsien-Hsin S. Lee, Xiaodong Wang, Dilip P. Vasudevan, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Static Average Case Power Estimation Technique for Block Ciphers

Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

ANovelMethodofTestGeneration forAsynchronous Circuits

Dilip P. Vasudevan, 2007 .

Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations

Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Reversible online BIST using bidirectional BILBO

Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens, 2010, CF '10.

3D photonics as enabling technology for deep 3D DRAM stacking

George Michelogiannakis, S. J. Ben Yoo, Pouya Fotouhi, 2019, MEMSYS.

CMOS realization of online testable reversible logic gates

Parag K. Lala, James Patrick Parkerson, Dilip P. Vasudevan, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

CASPER — Configurable design space exploration of programmable architectures for machine learning using beyond moore devices

John Shalf, David Donofrio, George Michelogiannakis, 2017, 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).