J. Delgado-Frías

发表

A dataflow approach for neural networks

G. G. Pechanek, S. Vassiliadis, J. Delgado-Frias, 1995 .

VLSI for Neural Networks and Artificial Intelligence

José G. Delgado-Frias, Will R. Moore, W. Moore, 1994, Springer US.

VLSI for Artificial Intelligence and Neural Networks

José G. Delgado-Frias, Will R. Moore, W. Moore, 1991, Springer US.

A neuro-emulator with embedded capabilities for generalized learning

Stamatis Vassiliadis, José G. Delgado-Frias, Gerald G. Pechanek, 1999, J. Syst. Archit..

Indirect interconnection networks for high performance routers/switches

José G. Delgado-Frias, Rongsen He, J. Delgado-Frías, 2007 .

Spin-L: sequential pipelined neuroemulator with learning capabilities

J.G. Delgado-Frias, S. Vassiliadis, G. G. Pechanek, 1993, Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan).

Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers

José G. Delgado-Frias, Rongsen He, J. Delgado-Frías, 2007, IEEE Transactions on Parallel and Distributed Systems.

A novel compaction scheme for routing tables in TCAM to enhance cache hit rate

José G. Delgado-Frias, R. Guo, J. Delgado-Frías, 2007, Communications, Internet, and Information Technology.

FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm

José G. Delgado-Frias, Jason Van Dyken, J. Delgado-Frías, 2010, J. Syst. Archit..

Autonomous management of a recursive area hierarchy for large scale wireless sensor networks using multiple parents

José G. Delgado-Frias, Johnathan Vee Cree, J. Cree, 2016, Ad Hoc Networks.

Management of large-scale wireless sensor networks utilizing multi-parent recursive area hierarchies

José G. Delgado-Frias, Johnathan Vee Cree, J. Cree, 2013, 2013 International Green Computing Conference Proceedings.

NOA: A Scalable Multi-Parent Clustering Hierarchy for WSNs

José G. Delgado-Frias, Mike Hughes, Johnathan Vee Cree, 2012, ANT/MobiWIS.

Delay and Energy Analysis of SEU and SET-Tolerant Pipeline Latches and Flip-Flops

J.G. Delgado-Frias, D.R. Blum, D. R. Blum, 2009, IEEE Transactions on Nuclear Science.

Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems

J.G. Delgado-Frias, D.R. Blum, D. R. Blum, 2006, IEEE Transactions on Nuclear Science.

Comparison of SET-Resistant Approaches for Memory-Based Architectures

José G. Delgado-Frias, Daniel R. Blum, D. R. Blum, 2005 .

Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance

José G. Delgado-Frias, Zhe Zhang, Michael A. Turi, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Near-Threshold CNTFET SRAM Cell Design With Word-Line Boosting and Removed Metallic CNT Tolerance

Jose G. Delgado-Frias, Zhe Zhang, Zhe Zhang, 2014, IEEE Transactions on Nanotechnology.

Near-threshold CNTFET SRAM cell design with gated cell power supply

Zhe Zhang, Jose G. Delgado-Frias, Zhe Zhang, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

CNTFET 8T SRAM cell performance with near-threshold power supply scaling

José G. Delgado-Frias, Zhe Zhang, Zhe Zhang, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

CNTFET SRAM cell with tolerance to removed metallic CNTs

Zhe Zhang, J. G. Delgado-Frias, Zhe Zhang, 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

Carbon Nanotube SRAM Design With Metallic CNT or Removed Metallic CNT Tolerant Approaches

Zhe Zhang, J. Delgado-Frias, J. Delgado-Frías, 2012, IEEE Transactions on Nanotechnology.

SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells

José G. Delgado-Frias, Zhe Zhang, Michael A. Turi, 2012, GLSVLSI '12.

Low power and metallic CNT tolerant CNTFET SRAM design

Zhe Zhang, J. Delgado-Frías, 2011, 2011 11th IEEE International Conference on Nanotechnology.

CNTFET SRAM cell design with tolerance to metallic CNTs

Jabulani Nyathi, Jose G. Delgado-Frias, Zhe Zhang, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Low power SRAM cell design for FinFET and CNTFET technologies

Zhe Zhang, Michael A. Turi, José G. Delgado-Frias, 2010, International Conference on Green Computing.

Performance of CNFET SRAM cells under diameter variation corners

Jabulani Nyathi, Jose G. Delgado-Frias, Zhe Zhang, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

High-Performance Low-Power Selective Precharge Schemes for Address Decoders

José G. Delgado-Frias, Michael A. Turi, M. A. Turi, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

A high performance hybrid wave-pipelined multiplier

José G. Delgado-Frias, Suryanarayana Tatapudi, J. Delgado-Frías, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

Jabulani Nyathi, J.G. Delgado-Frias, J. Lowe, 2003, 2003 46th Midwest Symposium on Circuits and Systems.

A hybrid wave pipelined network router

José G. Delgado-Frias, J. Nyathi, J. Nyathi, 2002 .

A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme

José G. Delgado-Frias, Suryanarayana Tatapudi, J. Delgado-Frías, 2005, CDES.

Computer architectures for artificial intelligence processing

J.G. Delgado-Frias, J. Delgado-Frías, 1990, IEEE Technical Conference on Southern Tier.

HYBRID NEWTON-RAPHSON GENETIC ALGORITHM FOR THE TRAVELING SALESMAN PROBLEM

S. Vassiliadis, J. Delgado-Frias, D. C. Gause, 1995 .

Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating

José G. Delgado-Frias, Michael A. Turi, M. A. Turi, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Full-VDD and near-threshold performance of 8T FinFET SRAM cells

José G. Delgado-Frias, Michael A. Turi, M. A. Turi, 2017, Integr..

Flexible oblivious router architecture

Stamatis Vassiliadis, José G. Delgado-Frias, Joonho Park, 1995, IBM J. Res. Dev..

Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers

Stamatis Vassiliadis, José G. Delgado-Frias, Joonho Park, 1994, Proceedings of Supercomputing '94.

Cache replacement policies for IP address lookups

Stephan Wong, José G. Delgado-Frias, Ruirui Guo, 2007 .

A Two-Level Reconfigurable Architecture for Digital Signal Processing

José G. Delgado-Frias, Mitchell J. Myjak, M. Myjak, 2007, VLSI.

High Performance Memory Read Using Cross-Coupled Pull-up Circuitry

J.G. Delgado-Frias, K. Blomster, J. Delgado-Frías, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

A mesochronous pipelining scheme for high-performance digital systems

José G. Delgado-Frias, Suryanarayana Tatapudi, J. Delgado-Frías, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

A high-performance encoder with priority lookahead

José G. Delgado-Frias, J. Nyathi, J. Nyathi, 2000 .

IP Routing table compaction and sampling schemes to enhance TCAM cache performance

José G. Delgado-Frias, Ruirui Guo, J. Delgado-Frías, 2009, J. Syst. Archit..

A high-performance low-power mesochronous pipeline architecture for computer systems

José G. Delgado-Frias, S. B. Tatapudi, J. Delgado-Frías, 2006 .

Online Firmware Functional Validation Scheme Using Colored Petri Net Model

Rahul Khanna, José G. Delgado-Frias, Yi Qian, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Executing tree routing algorithms on a high-performance pattern associative router

Stamatis Vassiliadis, José G. Delgado-Frias, Douglas H. Summerville, 1998, J. Syst. Archit..

A Pattern-Associative Router for Interconnection Network Adaptive Algorithms

José G. Delgado-Frias, Douglas H. Summerville, Daniel G. Rice, 1996, Euro-Par, Vol. I.

A Flexible Bit-Pattern Associative Router for Interconnection Networks

Stamatis Vassiliadis, José G. Delgado-Frias, Douglas H. Summerville, 1996, IEEE Trans. Parallel Distributed Syst..

A VLSI interconnection network router using a D-CAM with hidden refresh

José G. Delgado-Frias, Jabulani Nyathi, Douglas H. Summerville, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

A high performance pattern associative oblivious router for tree topologies

Stamatis Vassiliadis, José G. Delgado-Frias, Douglas H. Summerville, 1994, Proceedings of 8th International Parallel Processing Symposium.

A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks

José G. Delgado-Frias, Douglas H. Summerville, Rovy Sze, 1994, Proceedings of 4th Great Lakes Symposium on VLSI.

NXG05-1: Interleaved Multistage Switching Fabrics for Scalable High Performance Routers

José G. Delgado-Frias, Rongsen He, J. Delgado-Frías, 2006, IEEE Globecom 2006.

BVE: a wafer-scale engine for differential equation computation

José G. Delgado-Frias, D. M. Green, D. M. Green, 1988, ICS '88.

On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks

Li Zhao, José G. Delgado-Frias, Li Zhao, 2006, Wireless and Optical Communications.

Reducing power in memory decoders by means of selective precharge schemes

J.G. Delgado-Frias, M.A. Turi, M. A. Turi, 2007, 2007 50th Midwest Symposium on Circuits and Systems.

A Reduced Clock Delay Approach for High Performance Mesochronous Pipeline

J.G. Delgado-Frias, S.B. Tatapudi, J. Delgado-Frías, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Medium-Grain Cells for Reconfigurable DSP Hardware

José G. Delgado-Frias, Mitchell J. Myjak, M. Myjak, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

BASIS: A Biological Approach to System Information Security

Victor A. Skormin, José G. Delgado-Frias, Joseph Giordano, 2001, MMM-ACNS.