Jean Oudinot

SoC modelling for virtual prototyping with VHDL-AMS

Patricia Desgreys, Yannick Hervé, Jean Oudinot, 2004, FDL.

Scalable Model for Multi-Standard Phase Locked Loop

Jean Oudinot, Gilles Jacquemod, Benjamin Nicolle, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Top Verification of Low Power System with "Checkerboard" Approach

Jean Oudinot, 2006, PATMOS.

Application of Bottom-Up Methodology to RTW VCO

Jean Oudinot, Gilles Jacquemod, Benjamin Nicolle, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

Hierarchical Modeling of a Fractional Phase Locked Loop

Jean Oudinot, Gilles Jacquemod, Benjamin Nicolle, 2006, PATMOS.

VHDL-AMS library development for pacemaker applications

Jean Oudinot, B. Hecker, M. Chavassieux, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Speaking VHDL-AMS, a Newly Standarized Description Language, for Teaching Mixed Technology and Mixed Signal Systems

Thomas Zimmer, Noëlle Lewis, Jean Oudinot, 2000 .

Full Transceiver Circuit Simulation using VHDL-AMS

Jean Oudinot, Serge Scotti, Jean Ravatin, 2002, ESM.

Micromotor Simulation with VHDL-AMS

Jean-Yves Fourniols, Jean Oudinot, Marc P. Y. Desmulliez, 2003, FDL.

The Most Complete Mixed-Signal Simulation Solution with ADVance MS

Jean Oudinot, 2003, PATMOS.