S.D. Kulchycki

A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

D.K. Su, B.A. Wooley, S. Limotyrakis, 2005, IEEE Journal of Solid-State Circuits.

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $\Sigma \Delta$ Modulator

B.A. Wooley, K. Vleugels, S.D. Kulchycki, 2008, IEEE Journal of Solid-State Circuits.

A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator

B.A. Wooley, K. Vleugels, S.D. Kulchycki, 2007, 2007 IEEE Symposium on VLSI Circuits.

A 150MS/s 8b 71mW time-interleaved ADC in 0.18/spl mu/m CMOS

B.A. Wooley, S. Limotyrakis, S.D. Kulchycki, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).