Yi-Kan Cheng

发表

An efficient method for hot-spot identification in ULSI circuits

Sung-Mo Kang, Yi-Kan Cheng, 1999, ICCAD '99.

Fast thermal analysis for CMOS VLSIC reliability

Sung-Mo Kang, Yi-Kan Cheng, 1996, Proceedings of Custom Integrated Circuits Conference.

iTEM: a temperature-dependent electromigration reliability diagnosis tool

Sung-Mo Kang, Elyse Rosenbaum, Chin-Chi Teng, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An efficient full-chip ESD paths resistance value verification flow for large scale designs

Ming-Hsiang Song, Jen-Chou Tseng, Yi-Kan Cheng, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits

Chin-Cheng Kuo, Wei-Yi Hu, Yi-Kan Cheng, 2012, DAC Design Automation Conference 2012.

A temperature-aware simulation environment for reliable ULSI chipdesign

Sung-Mo Kang, Yi-Kan Cheng, S. Kang, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Configurable analog routing methodology via technology and design constraint unification

Hung-Ming Chen, Po-Cheng Pan, Wei-Yi Hu, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Application-based, transistor-level full-chip power analysis for 700 MHz PowerPC/sup TM/ microprocessor

David Bearden, Yi-Kan Cheng, Kanti Suryadevara, 2000, Proceedings 2000 International Conference on Computer Design.

Chip-level thermal simulator to predict VLSI chip temperature

Sung-Mo Kang, Yi-Kan Cheng, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Temperature-driven power and timing analysis for CMOS ULSI circuits

Sung-Mo Kang, Yi-Kan Cheng, S. Kang, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

ETS-A: a new electrothermal simulator for CMOS VLSI circuits

Sung-Mo Kang, Elyse Rosenbaum, Yi-Kan Cheng, 1996, Proceedings ED&TC European Design and Test Conference.

ICET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips

Sung-Mo Kang, Abhijit Dharchoudhury, Elyse Rosenbaum, 1996, DAC '96.

Electrothermal Analysis of VLSI Systems

Sung-Mo Kang, Ching-Han Tsai, Yi-Kan Cheng, 2000 .

DFM viewpoints of cell-level layout assessments and indications for concurrent layout optimization

Yi-Kan Cheng, Simon Klaver, Chung-Min Fu, 2008, Photomask Technology.

Hierarchical electromigration reliability diagnosis for VLSI interconnects

Sung-Mo Kang, Elyse Rosenbaum, Chin-Chi Teng, 1996, DAC '96.

A New Flexible Algorithm for Random Yield Improvement

Subarna Sinha, Qing Su, Yi-Kan Cheng, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

Sung-Mo Kang, Elyse Rosenbaum, Chin-Chi Teng, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Electrothermal Simulation and Temperature-Sensitive Reliability Diagnosis for CMOS VLSI Circuits

Yi-Kan Cheng, Yi-Kan Cheng, 1997 .

iCET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips

Sung-Mo Kang, Chin-Chi Teng, E. Rosenbaum, 1996, 33rd Design Automation Conference Proceedings, 1996.

Hierarchical electromigration reliability diagnosis for VLSI interconnects

Sung-Mo Kang, Chin-Chi Teng, E. Rosenbaum, 1996, 33rd Design Automation Conference Proceedings, 1996.