B. Chatterjee

Dual supply voltage clocking for 5 GHz 130 nm integer execution core

M. Sachdev, B. Bloechel, S. Borkar, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 90 nm 6.5 GHz 256/spl times/64 b dual supply register file with split decoder scheme

A. Alvandpour, M. Sachdev, S. Borkar, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).