Michael Meitinger

发表

Lastbalancierung und Resequenzierung in Netzwerkprozessoren

Michael Meitinger, Michael Meitinger, 2011 .

Reconfigurable Processing Units vs. Reconfigurable Interconnects

Michael Meitinger, Andreas Herkersdorf, Thomas Wild, 2006, Dynamically Reconfigurable Architectures.

Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications

Michael Meitinger, Andreas Herkersdorf, Thomas Wild, 2006, 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

A Processing Path Dispatcher in Network Processor MPSoCs

Michael Meitinger, Andreas Herkersdorf, Thomas Wild, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications

Michael Meitinger, Andreas Herkersdorf, Thomas Wild, 2007, J. Syst. Archit..

An Application-Aware Load Balancing Strategy for Network Processors

Michael Meitinger, Andreas Herkersdorf, Thomas Wild, 2010, HiPEAC.

A Hardware Packet Re-Sequencer Unit for Network Processors

Michael Meitinger, Andreas Herkersdorf, Thomas Wild, 2008, ARCS.

SPP1148 booth: Network processors

Michael Meitinger, Erik Maehle, Andreas Herkersdorf, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Hardware Support to Exploit Parallelism in Homogeneous and Heterogeneous Multi-Core Systems on Chip

Michael Meitinger, Andreas Herkersdorf, Andreas Lankes, 2010 .

Hardware Support for Efficient Resource Utilization in Manycore Processor Systems

Michael Meitinger, Andreas Herkersdorf, Andreas Lankes, 2011, Multiprocessor System-on-Chip.

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors

Michael Meitinger, Andreas Herkersdorf, Thomas Wild, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors

Michael Meitinger, Andreas Herkersdorf, Thomas Wild, 2010, Dynamically Reconfigurable Systems.

An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs

Michael Meitinger, Andreas Herkersdorf, Rainer Ohlendorf, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.