Motoshige Igarashi

A Novel STI Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond

Yuzuru Ohji, Kiyoteru Kobayashi, Masato Ishibashi, 2004 .

ALargeScale, Flip-Flop RAM imitating alogic LSI forfast development ofprocess technology

H. Makino, Miho Yokota, Tomohiro Tanaka, 2007 .

OS Technology with Five-Level Intercon using Al-plug and HSQ of Low-k for High Performance

Keiichi Higashitani, Katsuya Okada, Motoshige Igarashi, 1997 .

A dynamic body-biased SRAM with asymmetric halo implant MOSFETs

Hidehiro Fujiwara, Koji Nii, Makoto Yabuuchi, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Hybrid Cu and Al interconnects for high-performance system LSI

Hideaki Arima, Hiroyuki Amishiro, Motoshige Igarashi, 1999, Advanced Lithography.

A Large Scale, Flip-Flop RAM imitating a logic LSI for fast development of process technology

H. Makino, Miho Yokota, M. Fujii, 2007, ICMTS 2007.

A Large Scale, Flip-Flop RAM imitating a logic LSI for fast development of process technology

Koji Nii, Miho Yokota, Hiroshi Makino, 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology

Koji Nii, Shinji Tanaka, Noriaki Sakamoto, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

Improving SRAM read/write margin with asymmetric halo MOSFET

Hidehiro Fujiwara, Koji Nii, Makoto Yabuuchi, 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond

Y. Ohji, M. Inuishi, T. Kuroi, 2005 .