K. Reddy

Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter

Shanthi Pavan, Karthikeyan Reddy, S. Pavan, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter

Karthikeyan Reddy, Shanthi Pavan, S. Pavan, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications

Pavan Kumar Hanumolu, Karthikeyan Reddy, Sachin Rao, 2015, IEEE Journal of Solid-State Circuits.

A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators

Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A Deterministic Digital Background Calibration Technique for VCO-Based ADCs

Pavan Kumar Hanumolu, Brian Young, Karthikeyan Reddy, 2014, IEEE Journal of Solid-State Circuits.