Cosimo Antonio Prete

Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, 2010, 2010 22nd International Symposium on Computer Architecture and High Performance Computing.

Behavior investigation of concurrent Java programs: an approach based on source-code instrumentation

Cosimo Antonio Prete, Alessio Bechini, C. Prete, 2001, Future Gener. Comput. Syst..

MuTEAM: An experience in the design of robust multiprocessor systems

Paolo Corsini, Cosimo Antonio Prete, Luca Simoncini, 1985, Comput. Syst. Sci. Eng..

Reducing coherence-related overhead in multiprocessor systems

Luigi M. Ricciardi, Cosimo Antonio Prete, Gianpaolo Prina, 1995, Proceedings Euromicro Workshop on Parallel and Distributed Processing.

Software development environment for parallel systems

Beatrice Lazzerini, Paolo Corsini, Cosimo Antonio Prete, 1987 .

DISDEB: an interactive high-level debugging system for a multi-microprocessor system

Beatrice Lazzerini, Cosimo Antonio Prete, 1986 .

A hybrid approach to trace generation for performance evaluation of shared-bus multiprocessors

Luigi M. Ricciardi, Cosimo Antonio Prete, Roberto Giorgi, 1996, Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies.

Facing the False Miss Problem in D-NUCA based CMP Systems

Pierfrancesco Foglia, Cosimo Antonio Prete, Francesco Panicucci, 2008 .

Embedded processors and systems: Architectural issues and solutions for emerging applications

Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, 2006, J. Embed. Comput..

Optimizing instruction cache performance of embedded systems

Cosimo Antonio Prete, Sandro Bartolini, C. Prete, 2005, TECS.

CMP L2 NUCA Cache Energy Consumption Model

Pierfrancesco Foglia, Cosimo Antonio Prete, Francesco Panicucci, 2008 .

Hardware Architectures to Support real-time NURBS Interpolation

Alessandro Bardine, Stefano Campanelli, Pierfrancesco Foglia, 2010 .

ACM SIGARCH Computer Architecture news Special Issue: Proceedings of the MEDEA03 Workshop

Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, 2004 .

Improving power efficiency of D-NUCA caches

Per Stenström, Alessandro Bardine, Pierfrancesco Foglia, 2007, CARN.

Coherence in the CMP ERA: Lesson Learned in Designing a LLC Architecture

Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, 2014 .

Support for Architectural Design and Re-Design of Embedded Systems

Cosimo Antonio Prete, Alessio Bechini, 2005 .

MEDEA '08: Proc. 2008 workshop on MEmory performance

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2008 .

Introduction to Prolog computation model and its implementation

Beatrice Lazzerini, Cosimo Antonio Prete, Andrea Domenici, 1990 .

An object level transformation technique to improve the performance of embedded applications

Cosimo Antonio Prete, Sandro Bartolini, 2001, Proceedings First IEEE International Workshop on Source Code Analysis and Manipulation.

Row-level algorithm to improve real-time performance of glass tube defect detection in the production phase

Pierfrancesco Foglia, Cosimo Antonio Prete, Gabriele Antonio De Vitis, 2020, IET Image Process..

Assisting e-government users with animated talking faces

Pierfrancesco Foglia, Cosimo Antonio Prete, Michele Zanda, 2007, INTR.

Special track on Embedded Systems: Applications, Solutions, and Techniques: editorial message

Cosimo Antonio Prete, Alessio Bechini, 2008, SAC '08.

A kernel for a multiprocessor system with anonymous processes

Beatrice Lazzerini, Paolo Corsini, Cosimo Antonio Prete, 1988 .

A cache design for high performance embedded systems

Pierfrancesco Foglia, Cosimo Antonio Prete, Daniele Mangano, 2005, J. Embed. Comput..

Investigating Design Trade-Off in S-NUCA Based CMP Systems

Pierfrancesco Foglia, Cosimo Antonio Prete, Francesco Panicucci, 2009 .

A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems

Luigi M. Ricciardi, Cosimo Antonio Prete, Gianpaolo Prina, 1995, IEEE Trans. Parallel Distributed Syst..

PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors

Cosimo Antonio Prete, Roberto Giorgi, C. Prete, 1999, IEEE Trans. Parallel Distributed Syst..

Analysis of sharing overhead in shared memory multiprocessors

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 1998, Proceedings of the Thirty-First Hawaii International Conference on System Sciences.

Algorithms for the Detection of Blob Defects in High Speed Glass Tube Production Lines

Pierfrancesco Foglia, Cosimo Antonio Prete, Gabriele Antonio De Vitis, 2019, 2019 IEEE 8th International Workshop on Advances in Sensors and Interfaces (IWASI).

Impact of on-chip network parameters on nuca cache performances

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2009, IET Comput. Digit. Tech..

Performance‐steered design of software architectures for embedded multicore systems

Cosimo Antonio Prete, Alessio Bechini, C. Prete, 2002, Softw. Pract. Exp..

Simulation study of memory performance of SMP multiprocessors running a TPC-W workload

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2004 .

Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2005, J. Parallel Distributed Comput..

A process cache memory for tightly coupled multiprocessor systems

Cosimo Antonio Prete, C. Prete, 1992, ACM Southeast Regional Conference.

Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors

Luigi M. Ricciardi, Cosimo Antonio Prete, Roberto Giorgi, 1997, IEEE Concurrency.

Evaluating Power Consumption of D-Nuca Caches

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2007 .

Tuning D-Nuca Cache

Pierfrancesco Foglia, Cosimo Antonio Prete, Daniele Mangano, 2005 .

Leveraging Data Promotion for Low Power D-NUCA Caches

Per Stenström, Alessandro Bardine, Pierfrancesco Foglia, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

RST cache memory design for a highly coupled multiprocessor system

Cosimo Antonio Prete, C. Prete, 1991, IEEE Micro.

The ChARM tool for tuning embedded systems

Cosimo Antonio Prete, Marco Graziano, Francesco Lazzarini, 1997, IEEE Micro.

Integration of existing IEC 61131-3 systems in an IEC 61499 distributed solution

Stefano Campanelli, Pierfrancesco Foglia, Cosimo Antonio Prete, 2012, Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation (ETFA 2012).

Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction

Mateo Valero, Cosimo Antonio Prete, Roberto Giorgi, 2001, CARN.

Special Track on Embedded Systems: Across Hardware and Software

Cosimo Antonio Prete, Alessio Bechini, 2012, SAC 2012.

An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload

Pierfrancesco Foglia, Cosimo Antonio Prete, Francesco Panicucci, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

Accelerating DSS Workloads through Coherence Protocols

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2001 .

Analysis of static and dynamic energy consumption in NUCA caches: initial results

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2007, MEDEA '07.

Analysis of embedded video coder systems: a system-level approach

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2006, SIGARCH Comput. Archit. News.

A NUCA model for embedded systems cache design

Pierfrancesco Foglia, Cosimo Antonio Prete, Daniele Mangano, 2005, 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005..

A Synthetic trace generator for multiprocessor performance evaluation

Beatrice Lazzerini, Cosimo Antonio Prete, Andrea Domenici, 1989 .

A general model for an Abstract Prolog Machine

Beatrice Lazzerini, Cosimo Antonio Prete, Andrea Domenici, 1988 .

Implementation Issues of Way Adaptable D-NUCA Caches

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2008 .

NUCA caches: Analysis of Performance Sensitivity to NOC Parameters

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2008 .

Re-NUCA: Boosting CMP Performance Through Block Replication

Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

OS Effects on Memory Hierarchy of a SMP Multiprocessor Running a DBMS Workload

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2001 .

Guests editor's introduction

Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, 2005, SIGARCH Comput. Archit. News.

Eighth MEDEA Workshop

Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, 2011, Trans. High Perform. Embed. Archit. Compil..

Speeding-up multiprocessors running DBMS workloads through coherence protocols

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2004, Int. J. High Perform. Comput. Netw..

Special Track on Embedded Systems: Advances along the Hardware/Software Borderline

Cosimo Antonio Prete, Alessio Bechini, 2013, SAC 2013.

A Programmable Debugging Aid For

Lanfranco Lopriore, Beatrice Lazzerini, Cosimo Antonio Prete, 1986, IEEE Micro.

A Proposal for Distributed Commitment and Abort of Multi-Site Transactions in a Multi-Microprocessor System

Beatrice Lazzerini, Cosimo Antonio Prete, Paolo Ancilotti, 1986 .

Event treatment for program debugging in multi-microprocessor systems

Lanfranco Lopriore, Beatrice Lazzerini, Cosimo Antonio Prete, 1987 .

Modelling Public Administration Portals

Pierfrancesco Foglia, Cosimo Antonio Prete, Michele Zanda, 2007, Encyclopedia of Portal Technologies and Applications.

CMP L2 NUCA Cache Power Consumption Reduction Technique

Pierfrancesco Foglia, Cosimo Antonio Prete, Francesco Panicucci, 2008 .

Use of a CORBA/RMI gateway: characterization of communication overhead

Pierfrancesco Foglia, Cosimo Antonio Prete, Alessio Bechini, 2002, WOSP '02.

Techniques for Reducing Power Consumption in CMP NUCA Caches

Pierfrancesco Foglia, Cosimo Antonio Prete, Francesco Panicucci, 2007 .

A tool for testing of parallel and distributed programs in message-passing environments

Cosimo Antonio Prete, Alessio Bechini, J. Cutajar, 1998, MELECON '98. 9th Mediterranean Electrotechnical Conference. Proceedings (Cat. No.98CH36056).

Dynamic Optimization Techniques for D-NUCA Caches

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2008 .

An abstract Prolog machine

Beatrice Lazzerini, Cosimo Antonio Prete, Andrea Domenici, 1989 .

A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error

Alessandro Bardine, Stefano Campanelli, Pierfrancesco Foglia, 2012, Comput. Aided Des..

Evaluating optimizations for multiprocessors e-commerce server running TPC-W workload

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2001, Proceedings of the 34th Annual Hawaii International Conference on System Sciences.

Way Adaptable D-Nuca Cache

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2006 .

Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems

Cosimo Antonio Prete, Thomas M. Conte, Alessio Bechini, 2004, IEEE Micro.

An architecture to integrate IEC 61131-3 systems in an IEC 61499 distributed solution

Stefano Campanelli, Pierfrancesco Foglia, Cosimo Antonio Prete, 2015, Comput. Ind..

MEmory performance: DEaling with applications, systems and architecture

Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, 2007, CARN.

Editorial Message: Track on Embedded Systems

Cosimo Antonio Prete, Alessio Bechini, 2009, SAC 2009.

Fine-grain design space exploration for a cartographic SoC multiprocessor

Pierfrancesco Foglia, Cosimo Antonio Prete, Alessio Bechini, 2003, CARN.

Stock Price Forecasting Over Adaptive Timescale Using Supervised Learning and Receptive Fields

Gigliola Vaglini, Pierfrancesco Foglia, Cosimo Antonio Prete, 2018, MIKE.

An ESB implementation for airport environment

Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas, 2006 .

Event-driven debugging for distributed software

Beatrice Lazzerini, Cosimo Antonio Prete, C. Prete, 1988, Microprocess. Microsystems.

Analysis of Performance Dependencies in NUCA-Based CMP Systems

Pierfrancesco Foglia, Cosimo Antonio Prete, Francesco Panicucci, 2009, 2009 21st International Symposium on Computer Architecture and High Performance Computing.

Editorial message for the special track on embedded systems: applications, solutions, and techniques

Cosimo Antonio Prete, Alessio Bechini, 2004, SAC.

NUMA Caches

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2011, Encyclopedia of Parallel Computing.

A Prolog environment within the Unix operating system

Beatrice Lazzerini, Cosimo Antonio Prete, Andrea Domenici, 1987 .

PDA: un supporto hardware per un debugger interattivo e simbolico in un sistema multi-microprocessore

Lanfranco Lopriore, Beatrice Lazzerini, Cosimo Antonio Prete, 1985 .

Macchina Astratta di Warren e compilatore Prolog

Cosimo Antonio Prete, Andrea Domenici, 1993 .

Special Issue: Proceedings of the MEDEA02 Workshop

Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, 2003 .

Editorial Message: Special Track on Embedded Systems 2010

Cosimo Antonio Prete, Alessio Bechini, 2010 .

Performance analysis of electronic commerce multiprocessor server

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2000, Proceedings of the 33rd Annual Hawaii International Conference on System Sciences.

A Selective Invalidation Strategy for Cache Coherence

Luigi M. Ricciardi, Cosimo Antonio Prete, Gianpaolo Prina, 1995, IEICE Trans. Inf. Syst..

A cache-aware program transformation technique suitable for embedded systems

Cosimo Antonio Prete, Sandro Bartolini, C. Prete, 2002, Inf. Softw. Technol..

A Technique to Reduce the Processing Time of Defect Detection in Glass Tubes

Pierfrancesco Foglia, Cosimo Antonio Prete, Gabriele Antonio De Vitis, 2019, Advances in Intelligent Systems and Computing.

Cachesim: A Graphical Software Environment to Support the Teaching of Computer Systems with Cache Memories

Cosimo Antonio Prete, 1994, CSEE.

Memory performance: dealing with applications, systems and architecture

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2006, SIGARCH Comput. Archit. News.

A protocol for resource locking and deadlock detection in a multi-user environment

Beatrice Lazzerini, Cosimo Antonio Prete, Andrea Domenici, 1989 .

Way adaptable D-NUCA caches

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2010, Int. J. High Perform. Syst. Archit..

Editorial message for the special track on embedded systems: applications, solutions, and techniques

Cosimo Antonio Prete, Alessio Bechini, 2003, SAC '03.

Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems

Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, 2018, Future Gener. Comput. Syst..

An educational environment for program behavior analysis and cache memory design

Cosimo Antonio Prete, Roberto Giorgi, G. Prina, 1997, Proceedings Frontiers in Education 1997 27th Annual Conference. Teaching and Learning in an Era of Change.

An approach for investigating design and tuning performance of embedded systems

Cosimo Antonio Prete, Roberto Giorgi, G. Prina, 1997 .

Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture

Pierfrancesco Foglia, Cosimo Antonio Prete, Roberto Giorgi, 2002, NETWORKING Workshops.

A workload generation environment for trace-driven simulation of shared-bus multiprocessors

Luigi M. Ricciardi, Cosimo Antonio Prete, Roberto Giorgi, 1997, Proceedings of the Thirtieth Hawaii International Conference on System Sciences.

Performance Sensitivity of NUCA Caches to On-Chip Network Parameters

Alessandro Bardine, Pierfrancesco Foglia, Cosimo Antonio Prete, 2008, 2008 20th International Symposium on Computer Architecture and High Performance Computing.

Web-based training on computer architecture: the case for JCachesim

Cosimo Antonio Prete, Roberto Giorgi, Irina Branovic, 2002, WCAE '02.

Modelling Public Administration Portals: Requirements, Methodologies and Tools to improve the User Experience

Pierfrancesco Foglia, Cosimo Antonio Prete, M. Zanda, 2007 .

Editorial message for the special track on embedded systems: applications, solutions, and techniques

Cosimo Antonio Prete, Alessio Bechini, François Bodin, 2005, SAC '05.

Fast Blob and Air Line Defects Detection for High Speed Glass Tube Production Lines

Pierfrancesco Foglia, Cosimo Antonio Prete, Gabriele Antonio De Vitis, 2021, J. Imaging.

A pre-processing technique to decrease inspection time in glass tube production lines

Pierfrancesco Foglia, Cosimo Antonio Prete, Gabriele Antonio De Vitis, 2021, IET Image Process..