Z. Andales

VLSI architecture of burst mode acceleration for 128-bit block ciphers

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

VLSI implementation of dynamically reconfigurable hardware-based cryptosystem

T. Onoye, I. Shirakawa, Z. Andales, 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

Burst mode: a new acceleration mode for 128-bit block ciphers

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

VLSI implementation of high performance burst mode for 128-bit block ciphers

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

VLSI architecture of dynamically reconfigurable hardware-based cipher

Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).