N. Badereddine

A built-in scheme for testing and repairing voltage regulators of low-power srams

L. Dilillo, A. Bosio, A. Todri, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don't Care Bits Assignment

P. Girard, S. Pravossoudovitch, A. Virazel, 2006, 2006 Ph.D. Research in Microelectronics and Electronics.

Variability Analysis of an SRAM Test Chip

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2011, ETS 2011.

SRAM Core-cell Quality Metrics

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009 .

Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics

P. Girard, A. Virazel, C. Landrault, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Power-Aware Test Data Compression for Embedded IP Cores

P. Girard, A. Virazel, C. Landrault, 2006, 2006 15th Asian Test Symposium.