P. Madhani

Timing verification of dynamic circuits

Liang Chen, K. Venkat, I. Lin, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Timing verification of dynamic circuits

Liang Chen, P. Mistry, P. Madhani, 1996 .

0.1 /spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications

H. Shichijo, N. Mahalingam, J. Ai, 2002, Digest. International Electron Devices Meeting,.

Analog integration in a 0.35 /spl mu/m Cu metal pitch, 0.1 /spl mu/m gate length, low-power digital CMOS technology

H. Shichijo, R. Aggarwal, P. Madhani, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Mismatch characterization of a high precision resistor array test structure

P. Madhani, Weidong Tian, I. Khan, 2008, 2008 IEEE International Conference on Microelectronic Test Structures.

Impact of Sinter Process and Metal Coverage on Transistor Mismatching and Parameter Variations in Analog CMOS Technology

P. Madhani, J. Trogolo, Xiaoju Wu, 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

A 0.7 /spl mu/m linear BiCMOS/DMOS technology for mixed-signal/power applications

T. Efland, J. Erdeljac, L. Hutter, 1997, Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting.

Physics and modeling of transistor matching degradation under matched external stress

P. Madhani, Xiaoju Wu, Zhenwu Chen, 2008, 2008 IEEE International Conference on Microelectronic Test Structures.