Carlos Ornelas

A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS

Hyung Seok Kim, Ashoke Ravi, Krishnamurthy Soumyanath, 2012, 2012 IEEE International Solid-State Circuits Conference.

A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC

Hyung Seok Kim, Ashoke Ravi, Yee William Li, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

Hyung Seok Kim, Ashoke Ravi, Yee William Li, 2013, IEEE Journal of Solid-State Circuits.