Vinesh Srinivasan

Slipstream Processors Revisited: Exploiting Branch Sets

Eric Rotenberg, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor

Eric Rotenberg, Paul D. Franzon, William Rhett Davis, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

SCOC IP Cores for Custom Built Supercomputing Nodes

Karthikeyan P. Saravanan, Nachiappan Chidambaram Nachiappan, Ram Srivatsa Kannan, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor

Eric Rotenberg, Paul D. Franzon, Brandon H. Dwiel, 2015, 2015 IEEE Hot Chips 27 Symposium (HCS).

Schmitt Trigger based SRAM Cell for Ultralow Power Operation- A CNFET based Approach

K. Senthil Kumar, K. S. Kumar, Vinesh Srinivasan, 2013 .

Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores

Ram Srivatsa Kannan, Prashanth Thinakaran, Nagarajan Venkateswaran, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Phase II Implementation and Verification of the H3 Processor.

Vinesh Srinivasan, V. Srinivasan, 2015 .

Compilation Accelerator on Silicon

Karthikeyan P. Saravanan, Nachiappan Chidambaram Nachiappan, Ram Srivatsa Kannan, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.