Hiromitsu Awano

发表

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping

Makoto Ikeda, Yasuhiro Ogasahara, Yohei Hori, 2020, Integr..

PUFNet: A Deep Neural Network Based Modeling Attack for Physically Unclonable Function

Makoto Ikeda, Tomoki Iizuka, Hiromitsu Awano, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connections

Makoto Ikeda, Hiromitsu Awano, Keitaro Koga, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

PAPER Special Section on VLSI Design and CAD Algorithms Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method

Hiroyuki Ochi, Hiromitsu Awano, Hiroshi Tsutsui, 2012 .

Call Alternation Between Specific Pairs of Male Frogs Revealed by a Sound-Imaging Method in Their Natural Habitat

Hiroshi G. Okuno, Hiromitsu Awano, Ikkyu Aihara, 2016, INTERSPEECH.

ECRIPSE: An efficient method for calculating RTN-induced failure probability of an SRAM cell

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation

Takashi Sato, Hiromitsu Awano, Takashi Sato, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A study on parameter estimation for modeling of random-telegraph noise

Hiroyuki Ochi, Hiromitsu Awano, Hiroshi Tsutsui, 2011 .

Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs

Takashi Sato, Hiromitsu Awano, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Hardware Design of High Precision Discrete Gaussian Sampler for Lattice-based Cryptography

Makoto Ikeda, Hiromitsu Awano, Koga Keitaro, 2018 .

Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor

Makoto Ikeda, Hiromitsu Awano, Shotaro Sugiyama, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor Nodes

Makoto Ikeda, Hiromitsu Awano, Vinod V. Gadde, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Statistical aging under dynamic voltage scaling: A logarithmic model approach

Yu Cao, Takashi Sato, Hiromitsu Awano, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

Efficient circuit failure probability calculation along product lifetime considering device aging

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Workload-aware worst path analysis of processor-scale NBTI degradation

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

Multi-trap RTN parameter extraction based on Bayesian inference

Hiroyuki Ochi, Takashi Sato, Hiromitsu Awano, 2013, International Symposium on Quality Electronic Design (ISQED).

Automation of Model Parameter Estimation for Random Telegraph Noise

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Identification and Application of Invariant Critical Paths under NBTI Degradation

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Efficient transistor-level timing yield estimation via line sampling

Takashi Sato, Hiromitsu Awano, Takashi Sato, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method

Hiroyuki Ochi, Takashi Sato, Hiromitsu Awano, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices

Hiroyuki Ochi, Takashi Sato, Hiromitsu Awano, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

ASIC Coprocessor for 254-bit Prime-Field Pairing based on General Purpose Arithmetic Unit on Quadratic Extension Field

Hiromitsu Awano, Makoto Ikeda, 2018, 2018 International Conference on Advanced Technologies for Communications (ATC).

Swarm of Sound-to-Light Conversion Devices to Monitor Acoustic Communication Among Small Nocturnal Animals

Hiroshi G. Okuno, Takuma Otsuka, Hiromitsu Awano, 2017, J. Robotics Mechatronics.

BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA

Masanori Hashimoto, Hiromitsu Awano, H. Awano, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A scalable device array for statistical device-aging characterization

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Variability in device degradations: Statistical observation of NBTI for 3996 transistors

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

Recognition of In-Field Frog Chorusing Using Bayesian Nonparametric Microphone Array Processing

Katsutoshi Itoyama, Kazuyoshi Yoshii, Takuma Otsuka, 2015, AAAI Workshop: Computational Sustainability.

31.3 μs/Signature-Generation 256-bit 𝔽p ECDSA Cryptoprocessor

Makoto Ikeda, Hiromitsu Awano, Shotaro Sugiyama, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Human-robot cooperation in arrangement of objects using confidence measure of neuro-dynamical system

Tetsuya Ogata, Hiroshi G. Okuno, Shun Nishide, 2010, 2010 IEEE International Conference on Systems, Man and Cybernetics.

Compact Modeling of Statistical BTI Under Trapping/Detrapping

Yu Cao, Takashi Sato, Hiromitsu Awano, 2013, IEEE Transactions on Electron Devices.

Use of a Sparse Structure to Improve Learning Performance of Recurrent Neural Networks

Tetsuya Ogata, Hiroshi G. Okuno, Hiroaki Arie, 2011, ICONIP.

An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field

Makoto Ikeda, Hiromitsu Awano, Tadayuki Ichihashi, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Physically unclonable function using RTN-induced delay fluctuation in ring oscillators

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter

Hiromitsu Awano, Masanori Hashimoto, Dehua Liang, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Binary Neural Network in Robotic Manipulation: Flexible Object Manipulation for Humanoid Robot Using Partially Binarized Auto-Encoder on FPGA

Tetsuya Ogata, Hiromitsu Awano, Satoshi Ohara, 2021, 2021 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS).

Spatio-Temporal Dynamics in Collective Frog Choruses Examined by Mathematical Modeling and Field Observations

Kazuyuki Aihara, Takuma Otsuka, Hiromitsu Awano, 2014, Scientific Reports.

BTIarray: A Time-Overlapping Transistor Array for Efficient Statistical Characterization of Bias Temperature Instability

Takashi Sato, Hiromitsu Awano, Masayuki Hiromoto, 2014, IEEE Transactions on Device and Materials Reliability.