K. Mimoto

Interface socket design methodology to generate embedded DRAM macros

Shinji Miyano, Hiroyuki Takenaka, Ryo Haga, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

H. Takato, Shinji Miyano, Ryo Fukuda, 1999 .

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator

M. Wada, M. Enkaku, K. Sato, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

K. Numata, S. Miyano, T. Namekawa, 1999, IEEE Journal of Solid-State Circuits.