Yu Cao

Capturing device mismatch in analog and mixed-signal designs

A. Mitev, J. Wang, Yu Cao, 2008, IEEE Circuits and Systems Magazine.

Switch-factor based loop RLC modeling for efficient timing analysis

Yu Cao, D. Sylvester, Xiaodong Yang, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

Yu Cao, C. Spanos, Runzi Chang, 2004, IEEE Transactions on Electron Devices.