Watanabe Shigeyoshi

发表

Design Technology of stacked Type Chain PRAM

Kato Sho, Watanabe Shigeyoshi, 2011 .

Study of new stacked full adder circuit with fabrication technology of 3D flash memory.

Watanabe Shigeyoshi, Suzuki Fumiya, 2019 .

Study of new stacked type logic circuit scheme with fabrication technology of 3D flash memory

Watanabe Shigeyoshi, Suzuki Fumiya, 2019 .

Proplsal of reconfigurable system LSI with BiCS technology -- Application to combination logic, FF, CMOS circuit and FPGA

Watanabe Shigeyoshi, Tamai Shouto, Sato Takumi, 2017 .

Realistic future trend of non-volatile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory -- feasibility study of BiCS type FeRAM

Watanabe Shigeyoshi, Tamai Shouto, Sugano Koichi, 2008 .

Proposal of vertical stacked type Fe-FET NAND logic and its application to system LSI

Watanabe Shigeyoshi, Yokota Tomohiro, 2016 .

Design Technology of stacked Type Chain PRAM Readout

Kato Sho, Watanabe Shigeyoshi, 2012 .

Study of pattern area reduction with 3 dimensional transistor for logic circuit

Watanabe Shigeyoshi, Kodama Takahiro, Hiroshima Yu, 2011 .

Reducing pattern area technology of 3D transistor for system LSI

Watanabe Shigeyoshi, Hiroshima Yu, 2009 .

Energy comparison between various supply voltage scheme for System LSI

Watanabe Shigeyoshi, Hanami Satoshi, Kobayashi Manabu, 2007 .

Study of stacked NOR type MRAM for universal memory

Watanabe Shigeyoshi, Tamai Shouto, 2010 .

Study of high-speed low-power system LSI for sub-threshold operation

Watanabe Shigeyoshi, Tsurukubo Makoto, 2008 .

Design method of system LSI with low power device

Watanabe Shigeyoshi, Suzuki Ryosuke, 2011 .

Proposal of vertical stacked reconfigurable Fe-FET NAND logic and its application to combination logic, flip-flop and LUT

Watanabe Shigeyoshi, Sato Takumi, Yokota Tomohiro, 2016 .

Study of stacked type logic circuit with fabrication technology of 3D flash memory. -- Design of full adder and low power.

Watanabe Shigeyoshi, Suzuki Fumiya, 2019 .

Design method of stacked type NAND MRAM

Watanabe Shigeyoshi, Tamai Shoto, 2014 .

New design technology of independent-gate controlled Double-Gate transistor for LSI

Watanabe Shigeyoshi, Hiroshima Yu, Okamoto Keisuke, 2008 .

Study of pattern area and reconfigurable logic circuit with DG/CNT transistor

Watanabe Shigeyoshi, Hayashi Takamichi, 2012 .

Study of stacked type logic LSI with fabrication technology of 3D flash memory.

Watanabe Shigeyoshi, Suzuki Fumiya, 2020 .

Design Technology of stacked NAND type MRAM

Watanabe Shigeyoshi, Tamai Shouto, 2009 .

Circuit design of reconfigurable logic based on MOS double gate/Carbon Nano Tube transistor

Watanabe Shigeyoshi, Hayashi Takamichi, 2010 .