Seongjae Cho

发表

A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2009, IEEE Transactions on Nanotechnology.

Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering

Byung-Do Yang, Seongjae Cho, Yoon Kim, 2020, IEEE Access.

A New 1T DRAM Cell: Cone Type 1T DRAM Cell

Byung-Gook Park, Seongjae Cho, Doo-Hyun Kim, 2011, IEICE Trans. Electron..

Dependence of device performances on fin dimensions in AlGaN/GaN recessed-gate nanoscale FinFET

In Man Kang, Jae Hwa Seo, Seongjae Cho, 2014, The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014).

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2008, IEICE Trans. Electron..

InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate

In Man Kang, Jae Hwa Seo, Seongjae Cho, 2014, IEICE Trans. Electron..

Design and Simulation of Asymmetric MOSFETs

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2006, IEICE Trans. Electron..

Real-Time Intuitive Terrain Modeling by Mapping Video Images onto a Texture Database

Seongjae Cho, Kyhyun Um, Chee Sun Won, 2014 .

Investigation of Retention Characteristics Caused by Charge Loss for Charge Trap NAND Flash Memory

Byung-Gook Park, Seongjae Cho, Young-Min Kim, 2017 .

Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2014, IEICE Electron. Express.

Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

Il Han Park, Ki-Whan Song, Byung-Gook Park, 2006 .

Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications

In Man Kang, Jae Hwa Seo, Seongjae Cho, 2016 .

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009, IEICE Trans. Electron..

Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell

Byung-Gook Park, Seongjae Cho, Min-Hwi Kim, 2016, IEICE Trans. Electron..

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array

Hyungcheol Shin, Yoon Kim, Byung-Gook Park, 2009, IEICE Trans. Electron..

O2-Enhanced surface treatment of Ge epitaxially grown on Si for heterogeneous Ge technology

Byung-Gook Park, Seongjae Cho, James S. Harris, 2014, The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014).

A 2-Bit Recessed Channel Nonvolatile Memory Device With a Lifted Charge-Trapping Node

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2009 .

Quantitative Analysis on Voltage Schemes for Reliable Operations of a Floating Gate Type Double Gate Nonvolatile Memory Cell

Hyungcheol Shin, Il Han Park, Jong Duk Lee, 2005 .

Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer

Byung-Gook Park, Seongjae Cho, Kwon-Chil Kang, 2010, IEICE Trans. Electron..

Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs

In Man Kang, Seongjae Cho, Kyung Rok Kim, 2010, IEICE Electron. Express.

Fabrication and Characterization of a Fully Si Compatible Forming-Free GeOxResistive Switching Random-Access Memory

Il Hwan Cho, Seongjae Cho, Soo Gil Kim, 2018, 2018 76th Device Research Conference (DRC).

P/E Transient Modeling of NAND SONOS Flash Memories

Seongjae Cho, Doo-Hyun Kim, Byung-gook Park, 2007 .

Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory

Il Han Park, Byung-Gook Park, Seongjae Cho, 2009, SDM 2009.

Benefits of Arch Structure in Non-volatile Charge Trap Flash Memory

Il Han Park, Seongjae Cho, Se Hwan Park, 2007 .

Analyses on ZnO/CdS heterojunction for design of CIGS photovoltaic device with higher accuracy

Seongjae Cho, Sang Jik Kwon, Seong Min Lee, 2014, The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014).

Depletion-enhanced body-isolation (DEBI) array on SOI for highly scalable and reliable NAND flash memories

Il Han Park, Seongjae Cho, Jong Duk Lee, 2006 .

Continuous sensing of tumor-targeted molecular probes with a vertical cavity surface emitting laser-based biosensor

Sanjiv S. Gambhir, James S. Harris, Seongjae Cho, 2012, Journal of biomedical optics.

Evaluation of Radio-Frequency Performance of Gate-All-Around Ge/GaAs Heterojunction Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric by Mixed-Mode Simulation

In Man Kang, Jae Hwa Seo, Jung-Hee Lee, 2014 .

Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

In Man Kang, James S. Harris, Sang Wan Kim, 2010 .

A Silicon-Compatible Synaptic Transistor Capable of Multiple Synaptic Weights toward Energy-Efficient Neuromorphic Systems

Seongjae Cho, Byung-Gook Park, Eunseon Yu, 2019, Electronics.

Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance

In Man Kang, Min-Chul Sun, James S. Harris, 2012, IEICE Electron. Express.

A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical nor Array Structure

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2010, IEEE Transactions on Nanotechnology.

Memory characteristics improvement encouraged by the shape of narrow drain in cone SONOS memory structure

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Circuit-level simulation of resistive-switching random-access memory cross-point array based on a highly reliable compact model

Byung-Gook Park, Seongjae Cho, Min-Hwi Kim, 2018 .

Insertion of Ag Layer in TiN/SiNx/TiN RRAM and Its Effect on Filament Formation Modeled by Monte Carlo Simulation

Seongjae Cho, Sungjun Kim, Chae Soo Kim, 2020, IEEE Access.

Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs

Hyungcheol Shin, Seongjae Cho, Youngchang Yoon, 2007, IEICE Trans. Electron..

Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals

Byung-Gook Park, Seongjae Cho, Min-Hwi Kim, 2015, IEICE Trans. Electron..

A Novel Sensing Scheme for Reliable Read Operation of Ultrathin-Body Vertical nand Flash Memory Devices

Byung-Gook Park, Seongjae Cho, 2011, IEEE Transactions on Electron Devices.

Design optimization of an optically drivable heterogeneous MOSFET with silicon compatibility

S. J. Ben Yoo, James S. Harris, Byung-Gook Park, 2013, Photonics West - Optoelectronic Materials and Devices.

Investigation of Current Degradation Induced by Silicide Source/Drain in the nanowire NAND Flash Memory

Byung-Gook Park, Dae Woong Kwon, Seongjae Cho, 2010 .

Nanosculpture: Three-dimensional CMOS device structures for the ULSI era

Byung-Gook Park, Seongjae Cho, Hoon Jeong, 2009, Microelectron. J..

Fabrication Process of Cone SONOS Memory Structure

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

High-Speed Low-Power Junctionless Field-Effect Transistor with Ultra-Thin Poly-Si Channel for Sub-10-nm Technology Node

Junsoo Lee, Young-Min Kim, Seongjae Cho, 2016 .

DIBL-Induced Program Disturb Characteristics in 32-nm NAND Flash Memory Array

Myounggon Kang, Hyungcheol Shin, Il Han Park, 2011, IEEE Transactions on Electron Devices.

Surface Treatment of Ge Grown Epitaxially on Si by Ex-Situ Annealing for Optical Computing by Ge Technology

Byung-Gook Park, Seongjae Cho, James S. Harris, 2014 .

Process Considerations for 80-GHz High-Performance p-i-n Silicon Photodetector for Optical Interconnect

Min-Chul Sun, James S. Harris, Byung-Gook Park, 2012 .

Cone-Type SONOS Flash Memory

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2009, IEEE Electron Device Letters.

A Novel One-Transistor Dynamic Random-Access Memory (1T DRAM) Featuring Partially Inserted Wide-Bandgap Double Barriers for High-Temperature Applications

Il Hwan Cho, Seongjae Cho, Jae-Hee Han, 2018, Micromachines.

Simulation Study on Silicon-Based Floating Body Synaptic Transistor with Short- and Long-Term Memory Functions and Its Spike Timing-Dependent Plasticity

Min-Chul Sun, Byung-Gook Park, Seongjae Cho, 2016 .

Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications

In Man Kang, James S. Harris, Seongjae Cho, 2012 .

Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application

Byung-Gook Park, Seongjae Cho, Jang-Gn Yun, 2011 .

Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance

Hyungcheol Shin, Byung-Gook Park, Seongjae Cho, 2010, IEEE Electron Device Letters.

Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation

Byung-Gook Park, Jong Duk Lee, Seongjae Cho, 2009, IEICE Trans. Electron..

Enhanced Program/Erase Characteristic of Arch Shaped SONOS Flash Memory

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2007, IEICE Trans. Electron..

Validation of Spiking Neural Networks Using Resistive-Switching Synaptic Device with Spike-Rate-Dependent Plasticity

Seongjae Cho, Min-Hye Oh, Dong Keun Lee, 2020, 2020 International Conference on Electronics, Information, and Communication (ICEIC).

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

In Man Kang, Jae Hwa Seo, Jung-Hee Lee, 2014 .

Processing and Characterization of Ultra-thin Poly-crystalline Silicon for Memory and Logic Applications

Junsoo Lee, Young-Min Kim, Seongjae Cho, 2018 .

First-principle Study for More Accurate Optical and Electrical Characterization of Ge1-xSnx Alloy for Si and Group-IV Device Applications

Byung-Gook Park, Seongjae Cho, James S. Harris, 2017 .

Dependence of program and erase speed on bias conditions for fully depleted channel of vertical NAND flash memory devices

Byung-Gook Park, Seongjae Cho, Yoon Kim, 2009, 2009 10th Annual Non-Volatile Memory Technology Symposium (NVMTS).

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme

Yoon Kim, Byung-Gook Park, Jong Duk Lee, 2008, IEICE Trans. Electron..

Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

Kyungchul Park, Byung-Gook Park, Seongjae Cho, 2018, Journal of Applied Physics.

Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect

Byung-Gook Park, Seongjae Cho, Sae-Kyoung Kang, 2015, 2015 International Symposium on Consumer Electronics (ISCE).

Crystallization and Characterization of GeSn Deposited on Si with Ge Buffer Layer by Low-temperature Sputter Epitaxy

Dongsun Seo, Il Hwan Cho, Byung-Gook Park, 2016 .

Fabrication and characterization of fin SONOS flash memory with separated double-gate structure

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008 .

Gated Twin-Bit (GTB) nonvolatile memory device and its operation

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009, IEICE Trans. Electron..

Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

Byung-Gook Park, Seongjae Cho, Seung-Hyun Kim, 2016 .

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices

Hyungcheol Shin, Byung-Gook Park, Seongjae Cho, 2010, IEICE Trans. Electron..

Dependency of Program Efficiency on Implementation Conditions for NOR Type Silicon-on-Insulator (SOI) Flash Memory

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

Circuit-level macro modeling of charge-trap flash memory array

Byung-Gook Park, Seongjae Cho, Lee Sangho, 2017 .

Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology

Min-Chul Sun, James S. Harris, Byung-Gook Park, 2011 .

Pulse area dependent gradual resistance switching characteristics of CMOS compatible SiN x -based resistive memory

Byung-Gook Park, Seongjae Cho, Sungjun Kim, 2017 .

Compact modeling of silicon nanowire MOSFET for radio frequency applications

In Man Kang, Byung-Gook Park, Seongjae Cho, 2011 .

Tuning resistive switching parameters in Si3N4-based RRAM for three-dimensional vertical resistive memory applications

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2016 .

Effects of channel doping concentration and fin dimension variation on self-boosting of channel potential in NAND-type SONOS flash memory array based on bulk-FinFETs

Il Hwan Cho, Byung-Gook Park, Seongjae Cho, 2010 .

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

Byung-Gook Park, Seongjae Cho, Jang-Gn Yun, 2010 .

Effects of germanium incorporation on optical performances of silicon germanium passive devices for group-IV photonic integrated circuits

James S. Harris, Robert Sinclair, Byung-Gook Park, 2014 .

Channel doping concentration and fin width effects on self-boosting in NAND-type SONOS flash memory array based on bulk-FinFETs

Il Hwan Cho, Byung-Gook Park, Seongjae Cho, 2009, 2009 IEEE Nanotechnology Materials and Devices Conference.

Room-temperature electroluminescence from germanium in an Al(0.3)Ga(0.7)As/Ge heterojunction light-emitting diode by Γ-valley transport.

Byung-Gook Park, Seongjae Cho, Euijoon Yoon, 2012, Optics express.

Scaling Effect on Silicon Nitride Memristor with Highly Doped Si Substrate.

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2018, Small.

Gradual bipolar resistive switching in Ni/Si3N4/n+-Si resistive-switching memory device for high-density integration and low-power applications

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2015 .

Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

In Man Kang, Jae Hwa Seo, Seongjae Cho, 2013 .

Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation

In Man Kang, James S. Harris, Byung-Gook Park, 2011 .

Low-pressure, low-temperature hydrogen annealing for nanoscale silicon fin rounding

Byung-Gook Park, Seongjae Cho, Il Han Park, 2006, 2006 IEEE Nanotechnology Materials and Devices Conference.

Simulation for silicon-compatible InGaAs-based junctionless field-effect transistor using InP buffer layer

In Man Kang, Jae Hwa Seo, Seongjae Cho, 2013 .

Nano-cone resistive memory for ultralow power operation.

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2017, Nanotechnology.

Resistive switching characteristics of Si3N4-based resistive-switching random-access memory cell with tunnel barrier for high density integration and low-power applications

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2015 .

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

In Man Kang, Seongjae Cho, Seongjae Cho, 2012 .

Fully Si compatible SiN resistive switching memory with large self-rectification ratio

Byung-Gook Park, Seongjae Cho, Sungjun Kim, 2016 .

RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs

In Man Kang, Byung-Gook Park, Seongjae Cho, 2011, IEEE Transactions on Electron Devices.

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

In Man Kang, Jae Hwa Seo, Seongjae Cho, 2013 .

Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories

Hyungcheol Shin, Byung-Gook Park, Seongjae Cho, 2010 .

Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

In Man Kang, Jae Hwa Seo, Seongjae Cho, 2015 .

Characterization of 2-bit Recessed Channel Memory with Lifted Charge Trapping Node Scheme

Byung-Gook Park, Seongjae Cho, Il Han Park, 2007 .

Compound Semiconductor Tunneling Field-Effect Transistor Based on Ge/GaAs Heterojunction with Tunneling-Boost Layer for High-Performance Operation (Special Issue : Solid State Devices and Materials)

Jae Hwa Seo, Seongjae Cho, Young Jun Yoon, 2013 .

Compound Semiconductor Tunneling Field-Effect Transistor Based on Ge/GaAs Heterojunction with Tunneling-Boost Layer for High-Performance Operation

In Man Kang, Jae Hwa Seo, Byung-Gook Park, 2013 .

Effects of conducting defects on resistive switching characteristics of SiNx-based resistive random-access memory with MIS structure

Byung-Gook Park, Seongjae Cho, Sungjun Kim, 2015 .

Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Byung-Gook Park, Seongjae Cho, Meishoku Masahara, 2009, 2009 International Semiconductor Device Research Symposium.

Locally-separated vertical channel SONOS flash memory (LSVC SONOS) for multi-storage and multi-level operation

Byung-Gook Park, Seongjae Cho, Il Han Park, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Mixed-Mode Simulation of Nanowire Ge/GaAs Heterojunction Tunneling Field-Effect Transistor for Circuit Applications

In Man Kang, Byung-Gook Park, Seongjae Cho, 2013, IEEE Journal of the Electron Devices Society.

Ultrathin SiGe Shell Channel p-Type FinFET on Bulk Si for Sub-10-nm Technology Nodes

Seongjae Cho, Won-Jun Lee, Eunseon Yu, 2018, IEEE Transactions on Electron Devices.

A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency

Byung-Gook Park, Seongjae Cho, Hyungsoon Shin, 2019, IEEE Electron Device Letters.