Ting-Yen Chiang

Thermal analysis of heterogeneous 3D ICs with various integration scenarios

K.C. Saraswat, Chi On Chui, Ting-Yen Chiang, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

3-D ICS DSM Interconnect Performance Modeling and Analysis

Krishna C. Saraswat, Pawan Kapur, Ting-Yen Chiang, 2003 .

A new analytical thermal model for multilevel ULSI interconnects incorporating via effect

Kaustav Banerjee, Krishna C. Saraswat, Ting-Yen Chiang, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Closed-form analytical thermal model for accurate temperature estimation of multilevel ULSI interconnects

Ting-Yen Chiang, K.C. Saraswat, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

Impact of Joule Heating on Deep SubMicron Cu / low-k Interconnects

Ting-Yen Chiang, Ben Shieh, 2004 .

Impact of Joule heating on scaling of deep sub-micron Cu/low-k interconnects

Ting-Yen Chiang, K. Saraswat, K.C. Saraswat, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Effect of via separation and low-k dielectric materials on the thermal characteristics of Cu interconnects

Kaustav Banerjee, Krishna C. Saraswat, Ting-Yen Chiang, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Impact of vias on the thermal effect of deep sub-micron Cu/low-k interconnects

Ting-Yen Chiang, K.C. Saraswat, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).