Jörg Biesenack

The Siemens high-level synthesis system CALLAS

Jörg Biesenack, Michael Koster, Anton Langmaier, 1993, IEEE Trans. Very Large Scale Integr. Syst..

A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment

Norbert Wehn, Jörg Biesenack, Michael Pilsl, 1991, VLSI.

Scheduling of behavioral VHDL by retiming techniques

Norbert Wehn, Jörg Biesenack, Michael Pilsl, 1994, EURO-DAC '94.

Data Part Optimizations in the CALLAS Synthesis Environment

Norbert Wehn, Jörg Biesenack, A. Stoll, 1992, Synthesis for Control Dominated Circuits.

Flexible timing specification in a VHDL synthesis subset

Jörg Biesenack, Steffen Rumler, A. Stoll, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.