Peter Duzy

The Siemens high-level synthesis system CALLAS

Jörg Biesenack, Michael Koster, Anton Langmaier, 1993, IEEE Trans. Very Large Scale Integr. Syst..

High-level synthesis from VHDL with exact timing constraints

Peter Duzy, A. Stoll, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Scheduling of behavioral VHDL by retiming techniques

Norbert Wehn, Jörg Biesenack, Michael Pilsl, 1994, EURO-DAC '94.

The Synthesis Approach to Digital System Design

Peter Duzy, Petra Michel, U. Lauther, 1992 .

The CALLAS synthesis system and its application to mechatronic ASIC design problems

Peter Duzy, Peter Windirsch, P. Windirsch, 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.